Searched full:base_address (Results 1 – 6 of 6) sorted by relevance
9 base_address: 0x1101F00012 base_address: 0x3100000018 base_address: 0x500A4C0022 base_address: 0x5015C00024 base_address: 0x5009F00026 base_address: 0x5000200028 base_address: 0x3400000030 base_address: 0x500A000032 base_address: 0x5802100034 base_address: 0x500A5270[all …]
129 location_base_addresses[location] = data['locations'][location]['base_address']134 location_next_addresses[location] = data['locations'][location]['base_address'] + reserved_size
990 uint32_t base_address; in HAL_GTZC_MPCBB_ConfigMemAttributes() local1010 base_address = SRAM1_BASE_NS; in HAL_GTZC_MPCBB_ConfigMemAttributes()1016 base_address = SRAM1_BASE_S; in HAL_GTZC_MPCBB_ConfigMemAttributes()1022 base_address = SRAM2_BASE_NS; in HAL_GTZC_MPCBB_ConfigMemAttributes()1028 base_address = SRAM2_BASE_S; in HAL_GTZC_MPCBB_ConfigMemAttributes()1034 base_address = SRAM3_BASE_NS; in HAL_GTZC_MPCBB_ConfigMemAttributes()1040 base_address = SRAM3_BASE_S; in HAL_GTZC_MPCBB_ConfigMemAttributes()1046 base_address = SRAM4_BASE_NS; in HAL_GTZC_MPCBB_ConfigMemAttributes()1052 base_address = SRAM4_BASE_S; in HAL_GTZC_MPCBB_ConfigMemAttributes()1060 block_start = (MemAddress - base_address) / GTZC_MPCBB_BLOCK_SIZE; in HAL_GTZC_MPCBB_ConfigMemAttributes()[all …]
1027 uint32_t base_address; in HAL_GTZC_MPCBB_ConfigMemAttributes() local1047 base_address = SRAM1_BASE_NS; in HAL_GTZC_MPCBB_ConfigMemAttributes()1054 base_address = SRAM1_BASE_S; in HAL_GTZC_MPCBB_ConfigMemAttributes()1061 base_address = SRAM2_BASE_NS; in HAL_GTZC_MPCBB_ConfigMemAttributes()1068 base_address = SRAM2_BASE_S; in HAL_GTZC_MPCBB_ConfigMemAttributes()1076 base_address = SRAM3_BASE_NS; in HAL_GTZC_MPCBB_ConfigMemAttributes()1082 base_address = SRAM3_BASE_S; in HAL_GTZC_MPCBB_ConfigMemAttributes()1091 block_start = (MemAddress - base_address) / GTZC_MPCBB_BLOCK_SIZE; in HAL_GTZC_MPCBB_ConfigMemAttributes()1173 uint32_t base_address; in HAL_GTZC_MPCBB_GetConfigMemAttributes() local1192 base_address = SRAM1_BASE_NS; in HAL_GTZC_MPCBB_GetConfigMemAttributes()[all …]
835 uint32_t base_address, end_address; in HAL_GTZC_MPCBB_ConfigMemAttributes() local851 base_address = SRAM1_BASE_NS; in HAL_GTZC_MPCBB_ConfigMemAttributes()857 base_address = SRAM1_BASE_S; in HAL_GTZC_MPCBB_ConfigMemAttributes()863 base_address = SRAM2_BASE_NS; in HAL_GTZC_MPCBB_ConfigMemAttributes()869 base_address = SRAM2_BASE_S; in HAL_GTZC_MPCBB_ConfigMemAttributes()877 block_start = (MemAddress - base_address) / GTZC_MPCBB_BLOCK_SIZE; in HAL_GTZC_MPCBB_ConfigMemAttributes()930 uint32_t base_address, end_address; in HAL_GTZC_MPCBB_GetConfigMemAttributes() local946 base_address = SRAM1_BASE_NS; in HAL_GTZC_MPCBB_GetConfigMemAttributes()952 base_address = SRAM1_BASE_S; in HAL_GTZC_MPCBB_GetConfigMemAttributes()958 base_address = SRAM2_BASE_NS; in HAL_GTZC_MPCBB_GetConfigMemAttributes()[all …]
2862 \param [in] base_address Section base address2867 __STATIC_INLINE void MMU_TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t d… in MMU_TTSection() argument2873 offset = base_address >> 20; in MMU_TTSection()2874 entry = (base_address & 0xFFF00000) | descriptor_l1; in MMU_TTSection()2890 \param [in] base_address 4k base address2897 __STATIC_INLINE void MMU_TTPage4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t de… in MMU_TTPage4k() argument2904 offset = base_address >> 20; in MMU_TTPage4k()2912 offset2 = (base_address & 0xff000) >> 12; in MMU_TTPage4k()2914 entry2 = (base_address & 0xFFFFF000) | descriptor_l2; in MMU_TTPage4k()2926 \param [in] base_address 64k base address[all …]
