| /hal_intel-latest/bsp_sedi/drivers/i2c/ |
| D | sedi_i2c_dw_apb_200a.c | 66 uint32_t base; member
119 .base = SEDI_IREG_BASE(I2C, x), .speed = I2C_SPEED_FAST, \
151 static void dw_i2c_enable(uint32_t base) in dw_i2c_enable() argument
153 sedi_i2c_regs_t *i2c = (sedi_i2c_regs_t *)base; in dw_i2c_enable()
167 static int dw_i2c_disable(uint32_t base) in dw_i2c_disable() argument
169 sedi_i2c_regs_t *i2c = (sedi_i2c_regs_t *)base; in dw_i2c_disable()
194 static int dw_i2c_config_addr(uint32_t base, uint16_t slave_addr) in dw_i2c_config_addr() argument
196 sedi_i2c_regs_t *i2c = (sedi_i2c_regs_t *)base; in dw_i2c_config_addr()
206 static int dw_i2c_config_speed(uint32_t base, int speed, in dw_i2c_config_speed() argument
209 sedi_i2c_regs_t *i2c = (sedi_i2c_regs_t *)base; in dw_i2c_config_speed()
[all …]
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| /hal_intel-latest/bsp_sedi/drivers/spi/ |
| D | sedi_spi_dw_apb.c | 57 sedi_spi_regs_t *base; member
108 .base = (sedi_spi_regs_t *)SEDI_IREG_BASE(SPI, x), \
228 sedi_spi_regs_t *spi = context->base; in lld_spi_default_config()
321 sedi_spi_regs_t *spi = context->base; in lld_spi_set_transfer_mode()
342 sedi_spi_regs_t *spi = context->base; in lld_spi_fill_fifo()
486 sedi_spi_regs_t *spi = context->base; in dw_spi_set_start_condition()
536 INOUT void *param, IN uint32_t base) in sedi_spi_init() argument
549 context->base = (sedi_spi_regs_t *)base; in sedi_spi_init()
582 lld_spi_enable(context->base, false); in sedi_spi_set_power()
613 sedi_spi_regs_t *reg = context->base; in sedi_spi_get_status()
[all …]
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| /hal_intel-latest/bsp_sedi/drivers/gpio/ |
| D | sedi_gpio.c | 24 #define GPIO_SET_BIT(base, reg, index, bit) ((base->reg[index]) |= SET_MASK(bit)) argument
25 #define GPIO_CLEAR_BIT(base, reg, index, bit) ((base->reg[index]) &= CLEAR_MASK(bit)) argument
263 sedi_gpio_regs_t *base = resources_map[gpio_device].reg; in sedi_gpio_config_pin() local
268 GPIO_SET_BIT(base, gpdr, port, offset); in sedi_gpio_config_pin()
270 GPIO_CLEAR_BIT(base, gpdr, port, offset); in sedi_gpio_config_pin()
273 GPIO_CLEAR_BIT(base, gfer, port, offset); in sedi_gpio_config_pin()
274 GPIO_CLEAR_BIT(base, grer, port, offset); in sedi_gpio_config_pin()
277 GPIO_SET_BIT(base, gfer, port, offset); in sedi_gpio_config_pin()
281 GPIO_SET_BIT(base, grer, port, offset); in sedi_gpio_config_pin()
285 GPIO_SET_BIT(base, gimr, port, offset); in sedi_gpio_config_pin()
[all …]
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| /hal_intel-latest/bsp_sedi/soc/intel_ish/pm/ |
| D | ia_structs.h | 23 uint16_t base_addr_lw; /* base address (0:15) */
24 uint8_t base_addr_mb; /* base address (16:23) */
27 uint8_t base_addr_ub; /* base address (24:31) */
104 /* offset from TSS base for I/O perms */
128 #define GEN_GDT_DESC_LO(base, limit, flags) \ argument
129 ((((limit) >> 12) & 0xFFFF) | (((base) & 0xFFFF) << 16))
131 #define GEN_GDT_DESC_UP(base, limit, flags) \ argument
132 ((((base) >> 16) & 0xFF) | (((flags) << 8) & 0xFF00) | \
133 (((limit) >> 12) & 0xFF0000) | ((base) & 0xFF000000) | 0xc00000)
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| /hal_intel-latest/.github/workflows/ |
| D | checkpatch.yml | 29 - name: Set Git Base
32 git fetch origin ${{ github.event.pull_request.base.ref }}
33 echo "checkpatch base is: $(git show FETCH_HEAD --oneline --raw)"
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| /hal_intel-latest/bsp_sedi/soc/common/include/ |
| D | sedi_reg_defs.h | 28 * The constant for the register base address of instance <N> of a SEDI component IP
33 * The constant for the register base address of the only instance of a SEDI component IP
120 * - REGO (REGister address Offset): address offset from the IP base address.
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| /hal_intel-latest/bsp_sedi/include/driver/ |
| D | sedi_driver_spi.h | 360 * \param[in] base: base address of the SPI instance.
364 INOUT void *param, IN uint32_t base);
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| D | sedi_driver_i2c.h | 328 * \param[in] base: register base address of the i2c device.
332 IN uint32_t base);
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| D | sedi_driver_uart.h | 226 uint8_t *base; /* Start address. */ member
1175 * Set its register base address. A UART instance can be used only after
1179 * @param[in] register base address of the instance.
1184 int32_t sedi_uart_init(IN sedi_uart_t uart, void *base);
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| /hal_intel-latest/bsp_sedi/soc/intel_ish/pm/aon/ |
| D | aon_task.c | 134 * code : base = 0x0, limit = 0xFFFFFFFF, Present = 1, DPL = 0
135 * data : base = 0x0, limit = 0xFFFFFFFF, Present = 1, DPL = 0
141 * base: 0x0
155 * base: 0x0
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| /hal_intel-latest/bsp_sedi/soc/intel_ish/include/ |
| D | sedi_soc_regs.h | 22 /* UART register base addresses. */
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| /hal_intel-latest/bsp_sedi/drivers/usart/ |
| D | sedi_dw_uart.c | 298 vec_write_ctxt[uart].xfer.data = vec_xfer->vec[current_count].base; in io_vec_write_callback()
337 vec_read_ctxt[uart].xfer.data = vec_xfer->vec[current_count].base; in io_vec_read_callback()
1773 vec_write_ctxt[uart].xfer.data = vec_xfer->vec[0].base; in sedi_uart_write_vec_async()
1809 vec_read_ctxt[uart].xfer.data = vec_xfer->vec[0].base; in sedi_uart_read_vec_async()
2212 int32_t sedi_uart_init(IN sedi_uart_t uart, void *base) in sedi_uart_init() argument
2216 sedi_uart[uart] = (sedi_uart_regs_t *)base; in sedi_uart_init()
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| /hal_intel-latest/docs/ |
| D | bsp_sedi_doxyfile | 151 # operators of the base classes will not be shown.
532 # 'anonymous_namespace{file}', where file will be replaced with the base name of
1247 # that these files will be copied to the base HTML output directory. Use the
2286 # (in HTML and LaTeX) for classes with base or super classes. Setting the tag to
2317 # to run in parallel. When set to 0 doxygen will base this on the number of
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