| /Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/cavs/ |
| D | sram.c | 25 * Function powers up a number of memory banks provided as an argument
26 * and gates remaining memory banks
28 static __imr void hp_sram_pm_banks(uint32_t banks) in hp_sram_pm_banks() argument
40 * bit masks reflect total number of available EBB (banks) in each in hp_sram_pm_banks()
52 /* bit masks of banks that have to be powered up in each segment */ in hp_sram_pm_banks()
53 if (banks > EBB_SEG_SIZE) { in hp_sram_pm_banks()
55 ebb_mask1 = (uint32_t)GENMASK(banks - EBB_SEG_SIZE - 1, in hp_sram_pm_banks()
59 ebb_mask0 = (uint32_t)GENMASK(banks - 1, 0); in hp_sram_pm_banks()
103 * Calculate total number of used SRAM banks (EBB) in hp_sram_init()
104 * to power up only necessary banks in hp_sram_init()
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| /Zephyr-Core-3.5.0/drivers/memc/ |
| D | memc_sam_smc.c | 28 const struct memc_smc_bank_config *banks; member
49 if (cfg->banks[i].cs >= SMCCS_NUMBER_NUMBER) { in memc_smc_init()
53 bank = &cfg->regs->SMC_CS_NUMBER[cfg->banks[i].cs]; in memc_smc_init()
55 bank->SMC_SETUP = cfg->banks[i].setup_timing; in memc_smc_init()
56 bank->SMC_PULSE = cfg->banks[i].pulse_timing; in memc_smc_init()
57 bank->SMC_CYCLE = cfg->banks[i].cycle_timing; in memc_smc_init()
58 bank->SMC_MODE = cfg->banks[i].mode; in memc_smc_init()
99 .banks = smc_bank_config_##inst, \
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| D | memc_stm32_nor_psram.c | 32 const struct memc_stm32_nor_psram_bank_config *banks; member
96 memory_type = config->banks[bank_idx].init.MemoryType; in memc_stm32_nor_psram_init()
100 ret = memc_stm32_nor_init(config, &config->banks[bank_idx]); in memc_stm32_nor_psram_init()
105 ret = memc_stm32_psram_init(config, &config->banks[bank_idx]); in memc_stm32_nor_psram_init()
115 memory_type, config->banks[bank_idx].init.NSBank, ret); in memc_stm32_nor_psram_init()
171 .banks = bank_config,
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| D | memc_stm32_sdram.c | 32 const struct memc_stm32_sdram_bank_config *banks; member
47 memcpy(&sdram.Init, &config->banks[i].init, sizeof(sdram.Init)); in memc_stm32_sdram_init()
51 (FMC_SDRAM_TimingTypeDef *)&config->banks[i].timing); in memc_stm32_sdram_init()
57 } else if (config->banks[0].init.SDBank == FMC_SDRAM_BANK1) { in memc_stm32_sdram_init()
129 .banks = bank_config,
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| /Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/ace/ |
| D | comm_widget_messages.c | 15 * Report number of used HP-SRAM memory banks to the PMC, unit is 32 KB.
17 int adsp_comm_widget_pmc_send_ipc(uint16_t banks) in adsp_comm_widget_pmc_send_ipc() argument
23 FIELD_PREP(CW_PMC_IPC_SRAM_USED_BANKS, banks) | in adsp_comm_widget_pmc_send_ipc()
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| D | asm_memory_management.h | 6 * @brief Macros for power gating memory banks specific for ACE 1.0
38 movi \au, i_end - 1 /* au = banks count in segment */
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| D | pmc_interface.h | 72 * SRAM config - Any FW allocating HP-SRAM is expected to report allocated number of banks.
78 * Number of allocated HP-SRAM of banks, unit is 32 KB.
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| /Zephyr-Core-3.5.0/dts/bindings/flash_controller/ |
| D | gd,gd32-flash-controller.yaml | 10 GD32 FMC v2: its flash memory has 2 banks. Page size equal within the same bank but
11 different between banks. Flash size can be up to 3072KB. FMC v2 has two
14 GD32 FMC v3: its flash memory has 2 banks, use sector size as the minimum operating
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| /Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/ |
| D | adsp_comm_widget.h | 6 /* Report number of used HP-SRAM memory banks to the PMC, unit is 32 KB. */
7 int adsp_comm_widget_pmc_send_ipc(uint16_t banks);
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| /Zephyr-Core-3.5.0/include/zephyr/drivers/mm/ |
| D | mm_drv_intel_adsp_mtl_tlb.h | 14 * This function will save contents of the physical memory banks into a provided storage buffer
18 * Power states of memory banks will stay not touched
36 * This function will restore the contents and power state of the physical memory banks
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| D | mm_drv_bank.h | 9 * @brief Memory Banks Driver APIs
12 * driver to track page usage within memory banks. It is incumbent upon the
35 * The driver may wish to track various information about the memory banks
37 * that information. Since at the power on all memory banks are switched on
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| /Zephyr-Core-3.5.0/dts/bindings/memory-controllers/ |
| D | st,stm32-fmc-sdram.yaml | 8 memories. Up to 2 SDRAM banks are supported with independent configuration. It
13 The FMC SDRAM controller is defined below the FMC node and SDRAM banks are
132 - NB: Number of internal banks.
159 device in both banks.
164 programmed with the timing of the slowest device in both banks.
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| /Zephyr-Core-3.5.0/soc/arm/nxp_lpc/lpc55xxx/ |
| D | Kconfig.soc | 157 bool "CLock LPC SRAM banks"
161 By default, CMSIS SystemInit will enable the clock to these RAM banks.
162 Disable this Kconfig to leave the ram banks untouched out of reset.
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| D | CMakeLists.txt | 21 # CMSIS SystemInit allows us to skip enabling clock to SRAM banks via
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| /Zephyr-Core-3.5.0/drivers/can/ |
| D | Kconfig.stm32 | 25 filter banks.
41 filter banks.
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| /Zephyr-Core-3.5.0/drivers/mm/ |
| D | mm_drv_bank.c | 9 * @brief Module for tracking page use within memory banks
12 * to track page use within their memory banks. This information in turn
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| /Zephyr-Core-3.5.0/dts/bindings/gpio/ |
| D | xlnx,ps-gpio.yaml | 15 It is organized in banks, where the number of banks and total number
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| /Zephyr-Core-3.5.0/arch/arm/include/cortex_a_r/ |
| D | tcm.h | 29 * @brief Disable ECC on Tightly Coupled Memory Banks
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| /Zephyr-Core-3.5.0/soc/arc/snps_arc_hsdk4xd/ |
| D | Kconfig.defconfig | 22 # Actually cpu has 4 banks but zephys currently supports up to 2
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| /Zephyr-Core-3.5.0/include/zephyr/dt-bindings/memory-controller/ |
| D | stm32-fmc-sdram.h | 26 /* Number of internal banks */
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| /Zephyr-Core-3.5.0/drivers/gpio/ |
| D | gpio_xlnx_ps.h | 33 * addresses, references to all associated banks etc.) which don't
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| /Zephyr-Core-3.5.0/dts/bindings/qspi/ |
| D | st,stm32-qspi.yaml | 66 QSPI GPIO banks (defined as 'quadspi_bk[12]' in pinctrl property)
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| /Zephyr-Core-3.5.0/drivers/flash/ |
| D | flash_stm32l5x.c | 401 * which have space between banks 1 and 2. in flash_stm32_page_layout()
408 /* Dummy page corresponding to space between banks 1 and 2 */ in flash_stm32_page_layout()
421 * with 2MB flash which has no space between banks 1 and 2. in flash_stm32_page_layout()
428 /* Considering one layout of full flash size, even with 2 banks */ in flash_stm32_page_layout()
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| D | flash_stm32g0x.c | 25 * while only those with 256KiB and 512KiB Flash have two banks.
200 * two flash banks.
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| /Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/ |
| D | Kconfig | 90 Need to power cache SRAM banks on.
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