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Searched +full:apb1 +full:- +full:presacler (Results 1 – 3 of 3) sorted by relevance

/Zephyr-Core-3.6.0/dts/bindings/clock/
Dst,stm32wba-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
13 Core clock frequency should also be defined, using "clock-frequency" property.
21 ahb-prescaler = <2>;
22 clock-frequency = <DT_FREQ_M(40)>; /* = SYSCLK / AHB prescaler */
23 apb1-presacler = <1>;
24 apb2-presacler = <1>;
25 apb7-presacler = <7>;
55 compatible: "st,stm32wba-rcc"
57 include: [clock-controller.yaml, base.yaml]
63 "#clock-cells":
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Dst,stm32-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
13 Core clock frequency should also be defined, using "clock-frequency" property.
21 ahb-prescaler = <2>;
22 clock-frequency = <DT_FREQ_M(40)>; /* = SYSCLK / AHB prescaler */
23 apb1-presacler = <1>;
24 apb2-presacler = <1>;
70 compatible: "st,stm32-rcc"
72 include: [clock-controller.yaml, base.yaml]
78 "#clock-cells":
81 clock-frequency:
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/Zephyr-Core-3.6.0/drivers/clock_control/
Dclock_stm32_ll_h7.c7 * SPDX-License-Identifier: Apache-2.0
129 #error "APB1 frequency is too high!"
157 #error "D1CPRE presacler can't be higher than 1"
314 return -ERANGE; in get_vco_input_range()
356 return -ENOTSUP; in enabled_clock()
366 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) { in stm32_clock_control_on()
368 return -ENOTSUP; in stm32_clock_control_on()
373 sys_set_bits(STM32H7_BUS_CLK_REG + pclken->bus, pclken->enr); in stm32_clock_control_on()
387 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) { in stm32_clock_control_off()
389 return -ENOTSUP; in stm32_clock_control_off()
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