| /Zephyr-Core-3.5.0/dts/bindings/gpio/ |
| D | xlnx,xps-gpio-1.00.a.yaml | 3 compatible: "xlnx,xps-gpio-1.00.a"
5 include: [gpio-controller.yaml, base.yaml]
7 bus: xlnx,xps-gpio-1.00.a
10 # https://github.com/Xilinx/device-tree-xlnx
16 xlnx,all-inputs:
19 1 if all GPIOs are inputs, 0 otherwise
21 xlnx,all-outputs:
24 1 if all GPIOs are outputs, 0 otherwise
26 xlnx,dout-default:
29 Default output value. If n-th bit is 1, GPIO-n default value is 1.
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| /Zephyr-Core-3.5.0/boards/arm/arty/dts/ |
| D | arty_a7_arm_designstart.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/gpio/gpio.h>
9 #include <zephyr/dt-bindings/input/input-event-codes.h>
14 zephyr,shell-uart = &uartlite0;
29 spi-flash0 = &flash0;
33 compatible = "gpio-leds";
35 gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
95 gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
105 compatible = "gpio-keys";
117 gpios = <&gpio0_2 2 GPIO_ACTIVE_HIGH>;
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| /Zephyr-Core-3.5.0/doc/connectivity/bluetooth/api/mesh/ |
| D | blob_cli.rst | 18 .. code-block:: C
37 Inputs structure must at least be initialized with a list of targets, an application key and a time
40 .. code-block:: c
47 static struct bt_mesh_blob_cli_inputs inputs = {
52 sys_slist_init(&inputs.targets);
53 sys_slist_append(&inputs.targets, &targets[0].n);
54 sys_slist_append(&inputs.targets, &targets[1].n);
55 sys_slist_append(&inputs.targets, &targets[2].n);
57 Note that all BLOB Transfer Servers in the transfer must be bound to the chosen application key.
61 -------------
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| /Zephyr-Core-3.5.0/tests/bsim/bluetooth/mesh/src/ |
| D | test_blob.c | 4 * SPDX-License-Identifier: Apache-2.0
39 .option = "use-pull-mode", in test_args_parse()
46 .option = "msg-fail-type", in test_args_parse()
52 .name = "{inactive, start, wait-block, wait-chunk, complete, suspended}", in test_args_parse()
53 .option = "expected-phase", in test_args_parse()
79 partial_block += chunk->size; in blob_chunk_wr()
80 ASSERT_TRUE_MSG(partial_block <= block->size, "Received block is too large\n"); in blob_chunk_wr()
83 if (partial_block == block->size) { in blob_chunk_wr()
85 ASSERT_FALSE_MSG(atomic_test_and_set_bit(block_bitfield, block->number), in blob_chunk_wr()
105 memset(chunk->data, 0, chunk->size); in blob_chunk_rd()
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| D | test_dfu.c | 4 * SPDX-License-Identifier: Apache-2.0
74 .option = "fail-confirm", in test_args_parse()
80 .name = "{none, start, verify, verify-ok, verify-fail, apply}", in test_args_parse()
81 .option = "expected-phase", in test_args_parse()
109 memset(chunk->data, 0, chunk->size); in dummy_blob_chunk_rd()
182 return dfu_metadata_fail ? 0 : -1; in target_metadata_check()
197 return -EALREADY; in target_dfu_start()
314 BT_MESH_ELEM(2,
318 .elem_count = 2,
498 .ttl = 2, in dist_dfu_start_and_confirm()
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| /Zephyr-Core-3.5.0/dts/bindings/clock/ |
| D | atmel,sam-pmc.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 controlling all system and user peripheral clocks. The PMC enables/disables
9 the clock inputs to many of the peripherals and the processor.
16 clocks = <&pmc PMC_TYPE_PERIPHERAL p-id>;
20 In this example the clock-type was defined as PMC_TYPE_PERIPHERAL and the
21 peripheral-id was defined as p-id. The p-id number should be consulted on
27 The clock-type constants are:
34 compatible: "atmel,sam-pmc"
36 include: [clock-controller.yaml, base.yaml]
42 "#clock-cells":
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| /Zephyr-Core-3.5.0/dts/bindings/regulator/ |
| D | nxp,pca9420.yaml | 2 # SPDX -License-Identifier: Apache-2.0
7 The PMIC has two buck converters and two LDOs. All need to be defined as
15 /* all properties for BUCK1 */
18 /* all properties for BUCK2 */
21 /* all properties for LDO1 */
24 /* all properties for LDO2 */
34 nxp,enable-modesel-pins:
38 the MODESEL0/1 inputs.
40 nxp,vin-ilim-microamp:
44 - 85000
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| /Zephyr-Core-3.5.0/subsys/bluetooth/mesh/shell/ |
| D | blob.c | 4 * SPDX-License-Identifier: Apache-2.0
42 for (i = 0; i < chunk->size; ++i) { in blob_chunk_wr()
43 blob_rx_sum += chunk->data[i]; in blob_chunk_wr()
44 if (chunk->data[i] != in blob_chunk_wr()
45 blob_data[(i + chunk->offset) % sizeof(blob_data)]) { in blob_chunk_wr()
58 for (int i = 0; i < chunk->size; ++i) { in blob_chunk_rd()
59 chunk->data[i] = in blob_chunk_rd()
60 blob_data[(i + chunk->offset) % sizeof(blob_data)]; in blob_chunk_rd()
77 struct bt_mesh_blob_cli_inputs inputs; member
89 target->addr, reason); in blob_cli_lost_target()
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| D | dfd.c | 4 * SPDX-License-Identifier: Apache-2.0
22 shell_print(sh, "{\"status\": %d, \"target_cnt\": %d}", status, srv->target_cnt); in print_receivers_status()
29 srv->phase); in print_dfd_status()
31 if (srv->phase != BT_MESH_DFD_PHASE_IDLE && srv->dfu.xfer.slot) { in print_dfd_status()
34 "\"apply\": %d, \"slot_idx\": %d", srv->inputs.group, in print_dfd_status()
35 srv->inputs.app_idx, srv->inputs.ttl, srv->inputs.timeout_base, in print_dfd_status()
36 srv->dfu.xfer.blob.mode, srv->apply, srv->slot_idx); in print_dfd_status()
62 *total += slot->size; in slot_space_cb()
70 return -ENODEV; in cmd_dfd_receivers_add()
73 struct bt_mesh_dfd_srv *dfd_srv = mod->user_data; in cmd_dfd_receivers_add()
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| D | dfu.c | 4 * SPDX-License-Identifier: Apache-2.0
45 shell_print(bt_mesh_shell_ctx_shell, "DFU target lost: 0x%04x", target->blob.addr); in dfu_cli_lost_target()
115 return -EINVAL; in dfu_apply()
146 fwid->ver = img_header.h.v1.sem_ver; in bt_mesh_shell_dfu_cmds_init()
173 return -EINVAL; in cmd_dfu_comp_add()
179 return -EMSGSIZE; in cmd_dfu_comp_add()
205 return -EINVAL; in cmd_dfu_comp_elem_add()
210 sig_model_count = shell_strtoul(argv[2], 0, &err); in cmd_dfu_comp_elem_add()
213 if (argc < 4 + sig_model_count + vnd_model_count * 2) { in cmd_dfu_comp_elem_add()
214 return -EINVAL; in cmd_dfu_comp_elem_add()
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| /Zephyr-Core-3.5.0/drivers/interrupt_controller/ |
| D | Kconfig.multilevel | 5 # SPDX-License-Identifier: Apache-2.0
8 bool "Multi-level interrupt support"
14 all interrupts routed to it into one IRQ line in the first level
35 The maximum number of interrupt inputs to any aggregator in the
38 config 2ND_LEVEL_INTERRUPTS
39 bool "Second-level interrupt support"
45 config 2ND_LVL_ISR_TBL_OFFSET
46 int "Offset in _sw_isr_table for level 2 interrupts"
48 depends on 2ND_LEVEL_INTERRUPTS
51 where storage for 2nd level interrupt ISRs begins. This is
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| D | intc_dw_ace.c | 4 * SPDX-License-Identifier: Apache-2.0
20 /* ACE device interrupts are all packed into a single line on Xtensa's
24 * (i.e. interrupts 0-31 are Xtensa IRQs, 32 represents DW input 0,
28 * interrupt level of 2. The CPU has a level 1 external interrupt on
30 * that this level 2 ISR is also shared with the CCOUNT timer on IRQ3.
33 * But, because there can never be a situation where all interrupts on
37 * always has the line active, and we do all masking of external
48 * + Drivers manage ACE_DINT themselves, as there are device-specific
50 * core-asymmetric interrupt routing needs to happen, it happens
53 * + The DW layer is en/disabled uniformly across all cores. This is
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| /Zephyr-Core-3.5.0/subsys/bluetooth/mesh/ |
| D | blob_cli.c | 4 * SPDX-License-Identifier: Apache-2.0
19 SYS_SLIST_FOR_EACH_CONTAINER((sys_slist_t *)&(cli)->inputs->targets, \
24 /* The Maximum BLOB Poll Interval - T_MBPI */
27 #define CLIENT_TIMEOUT_MSEC(cli) (10 * MSEC_PER_SEC * (cli->inputs->timeout_base + 2) + \
28 100 * cli->inputs->ttl)
29 #define BLOCK_REPORT_TIME_MSEC ((BLOB_POLL_TIME_MAX_SECS * 2 + 7) * 1000)
32 #define SENDING_CHUNKS_IN_PULL_MODE(cli) ((cli)->state == BT_MESH_BLOB_CLI_STATE_BLOCK_SEND && \
33 (cli)->xfer->mode == BT_MESH_BLOB_XFER_MODE_PULL)
34 #define UNICAST_MODE(cli) ((cli)->inputs->group == BT_MESH_ADDR_UNASSIGNED || \
35 (cli)->tx.ctx.force_unicast)
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| D | dfu_cli.c | 4 * SPDX-License-Identifier: Apache-2.0
22 (sys_slist_t *)&((cli)->blob.inputs)->targets, target, blob.n)
26 .app_idx = (cli)->blob.inputs->app_idx, .addr = dst, \
27 .send_ttl = (cli)->blob.inputs->ttl, \
52 FLAG_SKIP_CAPS_GET = BIT(2),
77 if (addr == target->blob.addr) { in target_get()
89 target->status = status; in target_failed()
91 LOG_ERR("Target 0x%04x failed: %u", target->blob.addr, status); in target_failed()
96 if (target->blob.status == BT_MESH_BLOB_SUCCESS) { in target_failed()
97 target->blob.status = BT_MESH_BLOB_ERR_INTERNAL; in target_failed()
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| /Zephyr-Core-3.5.0/drivers/gpio/ |
| D | gpio_sifive.c | 2 * Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
4 * SPDX-License-Identifier: Apache-2.0
25 /* sifive GPIO register-set structure */
50 /* multi-level encoded interrupt corresponding to pin 0 */
64 ((const struct gpio_sifive_config * const)(dev)->config)
66 ((volatile struct gpio_sifive_t *)(DEV_GPIO_CFG(dev))->gpio_base_addr)
68 ((struct gpio_sifive_data *)(dev)->data)
79 } else if (level == 2) { in gpio_sifive_pin_irq()
93 if (level == 2) { in gpio_sifive_plic_to_pin()
97 return (plic_irq - base_irq); in gpio_sifive_plic_to_pin()
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| D | gpio_mchp_xec_v2.c | 4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/dt-bindings/gpio/gpio.h>
14 #include <zephyr/dt-bindings/pinctrl/mchp-xec-pinctrl.h>
49 /* Each GPIO pin 32-bit control register located consecutively in memory */
52 const struct gpio_xec_config *config = dev->config; in pin_ctrl_addr()
54 return config->pcr1_base + ((uintptr_t)pin * 4u); in pin_ctrl_addr()
57 /* GPIO Parallel input is a single 32-bit register per bank of 32 pins */
60 const struct gpio_xec_config *config = dev->config; in pin_parin_addr()
62 return config->parin_addr; in pin_parin_addr()
65 /* GPIO Parallel output is a single 32-bit register per bank of 32 pins */
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| D | gpio_pcal64xxa.c | 5 * SPDX-License-Identifier: Apache-2.0
114 struct pcal64xxa_drv_data *drv_data = dev->data; in pcal64xxa_pin_configure()
115 const struct pcal64xxa_drv_cfg *drv_cfg = dev->config; in pcal64xxa_pin_configure()
122 /* This device does not support open-source outputs, and open-drain in pcal64xxa_pin_configure()
123 * outputs can be only configured port-wise. in pcal64xxa_pin_configure()
126 return -ENOTSUP; in pcal64xxa_pin_configure()
129 /* Pins in this device can be either inputs or outputs and cannot be in pcal64xxa_pin_configure()
134 return -ENOTSUP; in pcal64xxa_pin_configure()
138 return -EWOULDBLOCK; in pcal64xxa_pin_configure()
141 k_sem_take(&drv_data->lock, K_FOREVER); in pcal64xxa_pin_configure()
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| /Zephyr-Core-3.5.0/boards/arc/em_starterkit/ |
| D | pmodmux.c | 4 * SPDX-License-Identifier: Apache-2.0
12 * 32-bits, offset 0x0, This register controls mapping of the peripheral device
16 /* 32-bits, offset 0x4 */
20 * 32-bits, offset 0x8, SPI_MAP_CTRL[0] selects the mode of operation of the SPI
22 * at connector J1. Loop-back mode, SPI_MAP_CTRL[0]=1: SPI Slave is connected to
25 #define SPI_MAP_CTRL 2
27 * 32-bits, offset 0x8, This register controls the mapping of the UART signals
34 #define BIT2 (2)
58 /* all pins are configured as GPIO inputs */
88 * Pmod3[2:1] are connected to DW GPIO Port D[1:0],
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| /Zephyr-Core-3.5.0/drivers/adc/ |
| D | adc_sam.c | 4 * SPDX-License-Identifier: Apache-2.0
46 * so all the channels would get repeated.
69 const struct adc_sam_config *const cfg = dev->config; in adc_sam_channel_setup()
70 Adc *const adc = cfg->regs; in adc_sam_channel_setup()
72 uint8_t channel_id = channel_cfg->channel_id; in adc_sam_channel_setup()
74 if (channel_cfg->differential) { in adc_sam_channel_setup()
75 if (channel_id != (channel_cfg->input_positive / 2U) in adc_sam_channel_setup()
76 || channel_id != (channel_cfg->input_negative / 2U)) { in adc_sam_channel_setup()
78 return -EINVAL; in adc_sam_channel_setup()
81 if (channel_id != channel_cfg->input_positive) { in adc_sam_channel_setup()
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| /Zephyr-Core-3.5.0/subsys/mgmt/osdp/ |
| D | Kconfig.pd | 4 # SPDX-License-Identifier: Apache-2.0
31 Address 0x7F is reserved as a broadcast address to which all PDs would
78 A 4-byte serial number for the PD.
86 - Bit 0-7 : build version number;
87 - Bit 8-15 : minor version number;
88 - Bit 16-23: major version number;
102 - 01: PD monitors and reports the state of the circuit without any
105 - 02: Like 01, plus: The PD accepts configuration of the encoding of the
108 - 03: Like 02, plus: PD supports supervised monitoring. The operating mode
110 - 04: Like 03, plus: the PD supports custom End-Of-Line settings within
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| /Zephyr-Core-3.5.0/doc/services/sensing/ |
| D | index.rst | 8 :depth: 2
22 report inputs.
38 protocols, the target is to support various up-layer frameworks and
40 such as `CHRE <https://github.com/zephyrproject-rtos/chre>`_, HID sensors Applications,
42 Applications with different up-layer sensor protocols at the same time
48 The diagram below illustrates how the Sensing Subsystem integrates with up-layer frameworks.
58 * Based on Zephyr existing low-level Sensor API (reuse 100+ existing sensor device drivers)
59 * Provide Zephyr high-level Sensing Subsystem API for Applications.
62 protocols (MQTT, HID or Private, all configurable)
81 * single thread main loop for all sensor objects sampling and process.
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| /Zephyr-Core-3.5.0/scripts/build/ |
| D | gen_app_partitions.py | 5 # SPDX-License-Identifier: Apache-2.0
10 Applications may declare build-time memory domain partitions with
13 route all their data into appropriately-sized memory areas which meet the
18 tool generates is a necessary pre-condition for kernel linking. We extract
24 This script takes as inputs:
26 - The base directory to look for compiled objects
27 - key/value pairs mapping static library files to what partitions their globals
55 SMEM_PARTITION_ALIGN(z_data_smem_{0}_bss_end - z_data_smem_{0}_part_start);
75 SMEM_PARTITION_ALIGN(z_data_smem_{0}_bss_end - z_data_smem_{0}_part_start);
104 z_data_smem_{0}_part_size = z_data_smem_{0}_part_end - z_data_smem_{0}_part_start;
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| /Zephyr-Core-3.5.0/boards/arm/bt610/doc/ |
| D | bt610.rst | 11 Cortex-M4F CPU.
19 * :abbr:`I2C (Inter-Integrated Circuit)`
28 * :abbr:`UART (Universal Asynchronous Receiver-Transmitter)`
55 +-----------+------------+----------------------+
58 | ADC | on-chip | adc |
59 +-----------+------------+----------------------+
60 | CLOCK | on-chip | clock_control |
61 +-----------+------------+----------------------+
62 | FLASH | on-chip | flash |
63 +-----------+------------+----------------------+
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| /Zephyr-Core-3.5.0/drivers/input/ |
| D | input_npcx_kbd.c | 5 * SPDX-License-Identifier: Apache-2.0
22 #define KEYBOARD_COLUMN_DRIVE_ALL -2
23 #define KEYBOARD_COLUMN_DRIVE_NONE -1
41 /* Keyboard scan input (KSI) wake-up irq */
43 /* Size of keyboard inputs-wui mapping array */
49 /* Mapping table between keyboard inputs and wui */
78 struct input_npcx_kbd_data *const data = dev->data; in input_npcx_kbd_ksi_isr()
80 k_sem_give(&data->poll_lock); in input_npcx_kbd_ksi_isr()
85 const struct input_npcx_kbd_config *const config = dev->config; in input_npcx_kbd_resume_detection()
88 irq_enable(config->irq); in input_npcx_kbd_resume_detection()
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| /Zephyr-Core-3.5.0/boards/arm/stm32373c_eval/doc/ |
| D | index.rst | 8 …e STM32373C-EVAL evaluation board is designed as a complete demonstration and development platform…
10 …ures on the board can help the user evaluate all peripherals (USB FS, USART, audio DAC, microphone…
16 :alt: STM32373C-EVAL
18 More information about the board can be found at the `STM32373C-EVAL website`_.
23 STM32373C-EVAL provides the following hardware components:
25 - STM32F373VCT6 microcontroller
26 - Four 5 V power supply options:
27 - Power jack
28 - ST-LINK/V2 USB connector
29 - User USB connector
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