Searched +full:ahb +full:- +full:packet +full:- +full:endian +full:- +full:swap (Results 1 – 2 of 2) sorted by relevance
3 # SPDX-License-Identifier: Apache-2.010 include: ethernet-controller.yaml19 clock-frequency:27 which it will be adjusted at run-time. Therefore, the value of this29 respective GEM's TX clock - by default, this is the IO PLL.31 mdc-divider:42 init-mdio-phy:45 Activates the management of a PHY associated with the controller in-46 stance. If this parameter is activated at the board level, the de-47 fault values of the associated parameters mdio-phy-address, phy-poll-[all …]
5 * SPDX-License-Identifier: Apache-2.08 * - Only supports 32-bit addresses in buffer descriptors, therefore9 * the ZynqMP APU (Cortex-A53 cores) may not be fully supported.10 * - Hardware timestamps not considered.11 * - VLAN tags not considered.12 * - Wake-on-LAN interrupt not supported.13 * - Send function is not SMP-capable (due to single TX done semaphore).14 * - Interrupt-driven PHY management not supported - polling only.15 * - No explicit placement of the DMA memory area(s) in either a18 * with the Cortex-R5 QEMU target or an actual R5 running without the[all …]
