Searched +full:ahb +full:- +full:boundary (Results 1 – 6 of 6) sorted by relevance
1 # Copyright 2018-2023, NXP2 # SPDX-License-Identifier: Apache-2.06 compatible: "nxp,imx-flexspi"8 include: [spi-controller.yaml, pinctrl-device.yaml]17 ahb-bufferable:20 Enable AHB bufferable write access by setting register field23 ahb-cacheable:26 Enable AHB cacheable read access by setting register field29 ahb-prefetch:32 Enable AHB read prefetch by setting register field AHBCR[PREFETCHEN].[all …]
4 * SPDX-License-Identifier: Apache-2.07 #include "frdm_rw612-pinctrl.dtsi"15 usart-0 = &flexcomm3;16 i2c-0 = &flexcomm2;17 pwm-0 = &sctimer;24 zephyr,shell-uart = &flexcomm3;28 compatible = "gpio-leds";36 compatible = "nxp,lpc-usart";38 current-speed = <115200>;39 pinctrl-0 = <&pinmux_flexcomm3_usart>;[all …]
2 * Copyright 2020-2023 NXP4 * SPDX-License-Identifier: Apache-2.027 read-while-write hazards. This configuration is not recommended."47 /* flexspi device data should be stored in RAM to avoid read-while-write hazards */75 struct memc_flexspi_data *data = dev->data; in memc_flexspi_wait_bus_idle()77 while (false == FLEXSPI_GetBusIdleStatus(data->base)) { in memc_flexspi_wait_bus_idle()83 struct memc_flexspi_data *data = dev->data; in memc_flexspi_is_running_xip()85 return data->xip; in memc_flexspi_is_running_xip()92 struct memc_flexspi_data *data = dev->data; in memc_flexspi_update_clock()98 * - disable the module in memc_flexspi_update_clock()[all …]
3 * SPDX-License-Identifier: Apache-2.058 /* Mask off bits[31:28] of 32-bit count */100 * on the AHB clock domain with the 32KHz clock domain of its internal logic.102 * depends upon which 48MHz AHB clock with a 32KHz period the register write103 * was on. We detect the timer is in the load state by checking the read-only130 * RTMR counter register is read-only and is loaded from the preload131 * register by a 0->1 transition of the control register start bit.142 uint32_t partial_cycles; /* number of cycles to first tick boundary */ in sys_clock_set_timeout()147 * global objects safe from pre-emption? in sys_clock_set_timeout()157 full_ticks = MAX_TICKS - 1; in sys_clock_set_timeout()[all …]
4 * SPDX-License-Identifier: Apache-2.067 * pcrs property at index 0 is register index into array of 32-bit PCR SLP_EN,77 /* Mask off bits[31:28] of 32-bit count */118 ECIA_XEC_REGS->GIRQ[girq - 8].SRC = BIT(bitpos); in girq_src_clr()127 ECIA_XEC_REGS->GIRQ[girq - 8].EN_SET = BIT(bitpos); in girq_src_en()136 ECIA_XEC_REGS->GIRQ[girq - 8].EN_CLR = BIT(bitpos); in girq_src_dis()141 TIMER_REGS->CTRL = 0U; in timer_restart()142 TIMER_REGS->CTRL = MCHP_RTMR_CTRL_BLK_EN; in timer_restart()143 TIMER_REGS->PRLD = countdown; in timer_restart()144 TIMER_REGS->CTRL = TIMER_START_VAL; in timer_restart()[all …]
6 * SPDX-License-Identifier: Apache-2.058 /* In dual-flash mode, total size is twice the size of one flash component */125 * If set addressed operations should use 32-bit rather than126 * 24-bit addresses.138 struct flash_stm32_qspi_data *dev_data = dev->data; in qspi_lock_thread()140 k_sem_take(&dev_data->sem, K_FOREVER); in qspi_lock_thread()145 struct flash_stm32_qspi_data *dev_data = dev->data; in qspi_unlock_thread()147 k_sem_give(&dev_data->sem); in qspi_unlock_thread()153 struct flash_stm32_qspi_data *dev_data = dev->data; in qspi_set_address_size()155 if (dev_data->flag_access_32bit) { in qspi_set_address_size()[all …]
