advertise\-lower\-link\-speeds (full) in projects: Zephyr-latest

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/Zephyr-latest/dts/bindings/ethernet/
D	xlnx,gem.yaml	`3 # SPDX-License-Identifier: Apache-2.0 10 include: ethernet-controller.yaml 19 clock-frequency: 26 is determined by the current link speed reported by the PHY, to 27 which it will be adjusted at run-time. Therefore, the value of this 29 respective GEM's TX clock - by default, this is the IO PLL. 31 mdc-divider: 42 init-mdio-phy: 45 Activates the management of a PHY associated with the controller in- 46 stance. If this parameter is activated at the board level, the de- [all …]`
/Zephyr-latest/drivers/ethernet/
D	phy_xlnx_gem.c	6 * - Marvell Alaska 88E1111 (QEMU simulated PHY) 7 * - Marvell Alaska 88E1510/88E1518/88E1512/88E1514 (Zedboard) 8 * - Texas Instruments TLK105 9 * - Texas Instruments DP83822 12 * SPDX-License-Identifier: Apache-2.0 34 * @return 16-bit data word received from the PHY 44 * MDIO read operation as described in Zynq-7000 TRM, in phy_xlnx_gem_mdio_read() 81 * Wait until gem.net_status[phy_mgmt_idle] == 1 -> current command in phy_xlnx_gem_mdio_read() 99 * Read the data returned by the PHY -> lower 16 bits of the PHY main- in phy_xlnx_gem_mdio_read() 113 * @param value 16-bit data word to be written to the target register [all …]