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/Zephyr-Core-3.5.0/subsys/shell/modules/
Ddevmem_service.c6 * SPDX-License-Identifier: Apache-2.0
39 static int memory_dump(const struct shell *sh, mem_addr_t phys_addr, size_t size, uint8_t width) in memory_dump() argument
44 const size_t vsize = width / BITS_PER_BYTE; in memory_dump()
56 addr += SHELL_HEXDUMP_BYTES_IN_LINE, size -= MIN(size, SHELL_HEXDUMP_BYTES_IN_LINE)) { in memory_dump()
60 switch (width) { in memory_dump()
90 shell_fprintf(sh, SHELL_NORMAL, "Incorrect data width\n"); in memory_dump()
91 return -EINVAL; in memory_dump()
104 size_t size = -1; in cmd_dump()
105 size_t width = 32; in cmd_dump() local
106 mem_addr_t addr = -1; in cmd_dump()
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/Zephyr-Core-3.5.0/dts/bindings/dma/
Dgd,gd32-dma-v1.yaml2 # SPDX-License-Identifier: Apache-2.0
12 - bit 6-7: Direction (see dma.h)
13 - 0x0: MEMORY to MEMORY
14 - 0x1: MEMORY to PERIPH
15 - 0x2: PERIPH to MEMORY
16 - 0x3: reserved for PERIPH to PERIPH
18 - bit 9: Peripheral address increase
19 - 0x0: no address increment between transfers
20 - 0x1: increment address between transfers
22 - bit 10: Memory address increase
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Dgd,gd32-dma.yaml2 # SPDX-License-Identifier: Apache-2.0
10 - bit 6-7: Direction (see dma.h)
11 - 0x0: MEMORY to MEMORY
12 - 0x1: MEMORY to PERIPH
13 - 0x2: PERIPH to MEMORY
14 - 0x3: reserved for PERIPH to PERIPH
16 - bit 9: Peripheral address increase
17 - 0x0: no address increment between transfers
18 - 0x1: increment address between transfers
20 - bit 10: Memory address increase
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/Zephyr-Core-3.5.0/boards/shields/x_nucleo_eeprma2/
Dx_nucleo_eeprma2.overlay4 * SPDX-License-Identifier: Apache-2.0
12 eeprom-0 = &eeprom0_x_nucleo_eeprma2;
13 eeprom-1 = &eeprom4_x_nucleo_eeprma2;
19 clock-frequency = <I2C_BITRATE_FAST>;
22 /* M24C02-FMC6TG aka U1 (2 kbit eeprom in DFN8 package) */
27 address-width = <8>;
30 /* if solder-bridge closed: arduino A1 pin on CN8 can wp */
31 /* wp-gpios = <&arduino_header 1 GPIO_ACTIVE_LOW>; */
35 /* M24256-DFDW6TP aka U2 (256 kbit eeprom in TSSOP package) */
40 address-width = <16>;
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/Zephyr-Core-3.5.0/tests/drivers/build_all/eeprom/
Dapp.overlay4 * SPDX-License-Identifier: Apache-2.0
9 * with real-world devicetree nodes, to allow these tests to run on
15 #address-cells = <1>;
16 #size-cells = <1>;
20 gpio-controller;
22 #gpio-cells = <0x2>;
27 #address-cells = <1>;
28 #size-cells = <0>;
32 clock-frequency = <100000>;
39 address-width = <16>;
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/Zephyr-Core-3.5.0/dts/bindings/mtd/
Datmel,at2x-base.yaml2 # SPDX-License-Identifier: Apache-2.0
6 include: eeprom-base.yaml
15 address-width:
18 description: EEPROM address width in bits
23 wp-gpios:
24 type: phandle-array
26 GPIO to which the write-protect pin of the chip is connected.
28 The device will interpret this signal as active-low.
Dfujitsu,mb85rcxx.yaml2 # SPDX-License-Identifier: Apache-2.0
8 include: ["eeprom-base.yaml", i2c-device.yaml]
21 address-width:
24 description: FRAM address width in bits.
26 wp-gpios:
27 type: phandle-array
28 description: GPIO to which the write-protect pin of the chip is connected.
/Zephyr-Core-3.5.0/tests/drivers/i2c/i2c_target_api/boards/
Dmimxrt1040_evk.overlay4 * SPDX-License-Identifier: Apache-2.0
11 * To test this sample, connect J17.9<->J17.3 (SDA), J17.10<->J17.6 (SCL)
22 address-width = <8>;
34 address-width = <8>;
/Zephyr-Core-3.5.0/drivers/watchdog/
Dwdt_dw.h1 /* SPDX-License-Identifier: Apache-2.0 */
19 * and programmed based on user-defined options.
116 * bits WDT_CNT_WIDTH - 1 to 0
190 * The Watchdog Timer counter width.
214 * Width of the APB Data Bus to which this component is attached.
219 * APB data width is 8 bits
224 * APB data width is 16 bits
229 * APB data width is 32 bits
241 * of 2 from 2^16 to 2^(WDT_CNT_WIDTH-1). When this parameter is set to 0, the user must define the
242 * timeout period range (2^8 to 2^(WDT_CNT_WIDTH)-1) using the WDT_USER_TOP_(i) parameter.
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/Zephyr-Core-3.5.0/soc/riscv/litex-vexriscv/
Dsoc.h2 * Copyright (c) 2018 - 2019 Antmicro <www.antmicro.com>
4 * SPDX-License-Identifier: Apache-2.0
10 #include "../riscv-privileged/common/soc_common.h"
22 #error CSR data width less than 8 in litex_read8()
34 #error Unsupported CSR data width in litex_read16()
48 #error Unsupported CSR data width in litex_read32()
68 #error Unsupported CSR data width in litex_read64()
77 #error CSR data width less than 8 in litex_write8()
89 #error Unsupported CSR data width in litex_write16()
103 #error Unsupported CSR data width in litex_write32()
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/Zephyr-Core-3.5.0/include/zephyr/drivers/misc/ft8xx/
Dft8xx_reference_api.h4 * SPDX-License-Identifier: Apache-2.0
44 * @param address Memory address to write to
47 static inline void wr8(uint32_t address, uint8_t data) in wr8() argument
49 ft8xx_wr8(address, data); in wr8()
55 * @param address Memory address to write to
58 static inline void wr16(uint32_t address, uint16_t data) in wr16() argument
60 ft8xx_wr16(address, data); in wr16()
66 * @param address Memory address to write to
69 static inline void wr32(uint32_t address, uint32_t data) in wr32() argument
71 ft8xx_wr32(address, data); in wr32()
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/Zephyr-Core-3.5.0/drivers/display/
Ddisplay_intel_multibootfb.c4 * This code attempts to be endian-agnostic. It manipulates the framebuffer
5 * address space only in 32-bit words (and assumes those words are 0xAARRGGBB).
7 * SPDX-License-Identifier: Apache-2.0
20 uint16_t width; member
31 return -ENOTSUP; in framebuf_blanking_on()
36 return -ENOTSUP; in framebuf_blanking_off()
47 return -ENOTSUP; in framebuf_set_brightness()
53 return -ENOTSUP; in framebuf_set_contrast()
63 return -ENOTSUP; in framebuf_set_pixel_format()
74 return -ENOTSUP; in framebuf_set_orientation()
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/Zephyr-Core-3.5.0/doc/_doxygen/
Dfooter.html1 <!-- HTML footer for doxygen 1.9.1-->
2 <!-- start footer part -->
3 <!--BEGIN GENERATE_TREEVIEW-->
4 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
7 …ww.doxygen.org/index.html"><img class="footer" src="$relpath^doxygen.svg" width="104" height="31" …
10 <!--END GENERATE_TREEVIEW-->
11 <!--BEGIN !GENERATE_TREEVIEW-->
12 <hr class="footer"/><address class="footer"><small>
13 …ww.doxygen.org/index.html"><img class="footer" src="$relpath^doxygen.svg" width="104" height="31" …
14 </small></address>
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/Zephyr-Core-3.5.0/drivers/ethernet/
DKconfig.nxp_s32_gmac1 # Copyright 2022-2023 NXP
2 # SPDX-License-Identifier: Apache-2.0
30 width.
47 width.
53 This option specifies the zero-based index of the clock configuration
88 bool "Multicast destination address filtering"
90 Enable support for multicast destination address filtering in the MAC.
91 MAC performs imperfect filtering using a 64-bit hash table. The upper
92 6-bits CRC of the received multicast address is used as index to the
/Zephyr-Core-3.5.0/samples/subsys/edac/
DREADME.rst1 .. zephyr:code-sample:: edac
3 :relevant-api: edac
19 .. zephyr-app-commands::
20 :zephyr-app: samples/subsys/edac
21 :host-os: unix
39 .. code-block:: console
41 uart:~$ edac -h
42 edac - EDAC information
51 .. code-block:: console
53 uart:~$ edac info -h
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/Zephyr-Core-3.5.0/drivers/dma/
Ddma_mcux_pxp.c5 * SPDX-License-Identifier: Apache-2.0
38 const struct dma_mcux_pxp_config *config = dev->config; in dma_mcux_pxp_irq_handler()
39 struct dma_mcux_pxp_data *data = dev->data; in dma_mcux_pxp_irq_handler()
41 PXP_ClearStatusFlags(config->base, kPXP_CompleteFlag); in dma_mcux_pxp_irq_handler()
43 DCACHE_InvalidateByRange((uint32_t) data->out_buf_addr, data->out_buf_size); in dma_mcux_pxp_irq_handler()
45 if (data->dma_callback) { in dma_mcux_pxp_irq_handler()
46 data->dma_callback(dev, data->user_data, 0, 0); in dma_mcux_pxp_irq_handler()
54 const struct dma_mcux_pxp_config *dev_config = dev->config; in dma_mcux_pxp_configure()
55 struct dma_mcux_pxp_data *dev_data = dev->data; in dma_mcux_pxp_configure()
62 if (config->channel_direction != MEMORY_TO_MEMORY) { in dma_mcux_pxp_configure()
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Ddma_mcux_lpc.c2 * Copyright (c) 2020-2023 NXP
4 * SPDX-License-Identifier: Apache-2.0
46 uint32_t width; member
68 ((DMA_Type *)((const struct dma_mcux_lpc_config *const)(dev)->config)->base)
71 ((struct channel_data *)(&(((struct dma_mcux_lpc_dma_data *)dev->data)->channel_data[ch])))
74 ((dma_handle_t *)(&(DEV_CHANNEL_DATA(dev, ch)->dma_handle)))
76 #define EMPTY_OTRIG -1
81 int ret = -EIO; in nxp_lpc_dma_callback()
83 uint32_t channel = handle->channel; in nxp_lpc_dma_callback()
93 data->busy = DMA_ChannelIsBusy(data->dma_handle.base, channel); in nxp_lpc_dma_callback()
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/Zephyr-Core-3.5.0/dts/bindings/flash_controller/
Dst,stm32-qspi-nor.yaml2 # SPDX-License-Identifier: Apache-2.0
9 mx25r6435f: qspi-nor-flash@0 {
10 compatible = "st,stm32-qspi-nor";
12 qspi-max-frequency = <80000000>;
14 reset-gpios = <&gpiod 3 GPIO_ACTIVE_LOW>;
15 reset-gpios-duration = <1>;
16 spi-bus-width = <4>;
20 compatible: "st,stm32-qspi-nor"
22 include: ["flash-controller.yaml", "jedec,jesd216.yaml"]
24 on-bus: qspi
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/Zephyr-Core-3.5.0/drivers/syscon/
Dsyscon_common.h3 * SPDX-License-Identifier: Apache-2.0
16 * @brief Align and check register address
18 * @param reg Pointer to the register address in question.
20 * @param reg_width The width of a single register (in bytes).
22 * @return -EINVAL is the read is invalid.
29 /* Check for out-of-bounds readings */ in syscon_sanitize_reg()
31 return -EINVAL; in syscon_sanitize_reg()
/Zephyr-Core-3.5.0/tests/drivers/eeprom/api/boards/
Dnative_posix.overlay2 * SPDX-License-Identifier: Apache-2.0
7 eeprom-1 = &i2c_eeprom;
17 address-width = <8>;
Dmr_canhubk3.overlay4 * SPDX-License-Identifier: Apache-2.0
7 /* Connect I2C0 (connector P4) to the external eeprom Microchip AT24C01C-XHM */
11 eeprom-0 = &eeprom0;
22 address-width = <8>;
/Zephyr-Core-3.5.0/include/zephyr/dt-bindings/memory-controller/
Dstm32-fmc-sdram.h4 * SPDX-License-Identifier: Apache-2.0
10 /* Number of column address bits */
16 /* Number of row address bits */
21 /* Memory data bus width. */
/Zephyr-Core-3.5.0/dts/arm/xilinx/
Dzynqmp.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-r.dtsi>
9 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
10 #include <zephyr/dt-bindings/ethernet/xlnx_gem.h>
15 compatible = "soc-nv-flash";
20 compatible = "mmio-sram";
25 compatible = "zephyr,memory-region", "xlnx,zynq-ocm";
27 zephyr,memory-region = "OCM";
36 interrupt-names = "irq_0";
45 interrupt-names = "irq_0";
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/Zephyr-Core-3.5.0/boards/arm/arty/dts/
Darty_a7_arm_designstart.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/gpio/gpio.h>
9 #include <zephyr/dt-bindings/input/input-event-codes.h>
14 zephyr,shell-uart = &uartlite0;
29 spi-flash0 = &flash0;
33 compatible = "gpio-leds";
105 compatible = "gpio-keys";
149 compatible = "arm,daplink-qspi-mux";
151 interrupt-parent = <&nvic>;
153 mux-gpios = <&daplink_gpio0 0 GPIO_ACTIVE_HIGH>;
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/Zephyr-Core-3.5.0/dts/arm/nordic/
Dnrf52832.dtsi1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <arm/armv7-m.dtsi>
9 zephyr,flash-controller = &flash_controller;
13 #address-cells = <1>;
14 #size-cells = <0>;
18 compatible = "arm,cortex-m4f";
20 #address-cells = <1>;
21 #size-cells = <1>;
24 compatible = "arm,armv7m-itm";
26 swo-ref-frequency = <32000000>;
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