Searched full:xilinx (Results 1 – 25 of 91) sorted by relevance
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| /Zephyr-Core-3.5.0/drivers/serial/ |
| D | Kconfig.xlnx | 1 # Xilinx UART configuration
3 # Copyright (c) 2018 Xilinx Inc.
7 bool "Xilinx Zynq 7000/ZynqMP serial driver"
13 This option enables the UART driver for Xilinx MPSoC platforms.
16 bool "Xilinx UART Lite"
22 This option enables the UART driver for Xilinx UART Lite IP.
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| /Zephyr-Core-3.5.0/drivers/watchdog/ |
| D | Kconfig.xlnx | 1 # Xilinx watchdog configuration
7 bool "Xilinx AXI Timebase WDT driver"
11 Enable the Xilinx AXI Timebase WDT driver.
16 bool "Expose HWINFO API in Xilinx AXI Timebase WDT driver"
20 Controls whether the Xilinx AXI Timebase WDT driver exposes a HWINFO
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| /Zephyr-Core-3.5.0/dts/bindings/ipm/ |
| D | xlnx,zynqmp-ipi-mailbox.yaml | 4 The Xilinx IPI(Inter Processor Interrupt) mailbox controller is to manage
5 messaging between two Xilinx Zynq UltraScale+ MPSoC IPI agents. Each IPI
24 description: Host Xilinx IPI agent ID of which the mailbox is connected to.
28 description: Xilinx IPI agent child node
44 Remote Xilinx IPI agent ID of which the mailbox is connected to.
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| /Zephyr-Core-3.5.0/drivers/gpio/ |
| D | Kconfig.xlnx | 1 # Xilinx GPIO configuration options
7 bool "Xilinx AXI GPIO driver"
11 Enable Xilinx AXI GPIO v2 driver.
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| D | Kconfig.xlnx_ps | 2 # Xilinx Processor System MIO / EMIO GPIO controller driver
10 bool "Xilinx Processor System MIO / EMIO GPIO controller driver"
15 Enable the Xilinx Processor System MIO / EMIO GPIO controller driver.
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| D | gpio_xlnx_ps.c | 2 * Xilinx Processor System MIO / EMIO GPIO controller driver
30 * @brief Initialize a Xilinx PS GPIO controller parent device
32 * Initialize a Xilinx PS GPIO controller parent device, whose task it is
53 * @brief Xilinx PS GPIO controller parent device ISR
55 * Interrupt service routine for the Xilinx PS GPIO controller's
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| /Zephyr-Core-3.5.0/drivers/spi/ |
| D | Kconfig.xlnx | 1 # Xilinx SPI
7 bool "Xilinx AXI Quad SPI driver"
11 Enable Xilinx AXI Quad SPI v3.2 driver.
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| /Zephyr-Core-3.5.0/drivers/counter/ |
| D | Kconfig.xlnx | 1 # Xilinx AXI Timer
7 bool "Xilinx AXI Timer driver"
11 Enable counter support for the Xilinx AXI Timer v2.0 IP.
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| /Zephyr-Core-3.5.0/drivers/pwm/ |
| D | Kconfig.xlnx | 1 # Xilinx AXI Timer
7 bool "Xilinx AXI Timer driver"
11 Enable PWM support for the Xilinx AXI Timer v2.0 IP.
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| /Zephyr-Core-3.5.0/drivers/i2c/ |
| D | Kconfig.xilinx_axi | 5 bool "Xilinx AXI I2C driver"
10 Enable the Xilinx AXI IIC Bus Interface driver.
11 This is an FPGA logic core as described by Xilinx document PG090.
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| /Zephyr-Core-3.5.0/drivers/ethernet/ |
| D | Kconfig.xlnx_gem | 2 # Xilinx Processor System Gigabit Ethernet controller (GEM) driver
10 bool "Xilinx GEM Ethernet driver"
15 Enable Xilinx GEM Ethernet driver.
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| /Zephyr-Core-3.5.0/drivers/timer/ |
| D | Kconfig.xlnx_psttc | 7 bool "Xilinx PS ttc timer support"
12 This module implements a kernel device driver for the Xilinx ZynqMP
17 int "Xilinx PS ttc timer index"
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| /Zephyr-Core-3.5.0/boards/arm/kv260_r5/doc/ |
| D | index.rst | 3 Xilinx KV260 Development Board RPU Cortex-R5
8 This configuration provides support for the RPU, real-time processing unit on Xilinx
17 * Xilinx Zynq TTC (Cadence TTC)
18 * Xilinx Zynq UART
22 :alt: Xilinx KV260 Starter Kit
72 * Xilinx Zynq TTC driver does not support tickless mode operation.
81 Users can make use of Xilinx's pre-built Petalinux reference images as a starting point to enable
82 remoteproc support, it is based around 5.15 Xilinx maintained kernel, as described here:
84 https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/1641152513/Kria+K26+SOM#PetaLinux
91 Select the option ``xilinx-kv260.tar.gz``, and just decompress it to the target rootfs
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| /Zephyr-Core-3.5.0/dts/bindings/rtc/ |
| D | xlnx,xps-timer-1.00.a.yaml | 1 description: Xilinx AXI Timer IP node
7 # Property names correspond to those used by Xilinx PetaLinux:
8 # https://github.com/Xilinx/meta-xilinx
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| /Zephyr-Core-3.5.0/boards/arm/arty/doc/ |
| D | index.rst | 11 different Xilinx FPGA (Spartan-7, Artix-7, or Zynq-7000 series).
31 DesignStart FPGA`_ Xilinx edition reference designs from ARM. Zephyr supports
41 - `Technical Resources for DesignStart FPGA on Xilinx`_
42 - `ARM DesignStart FPGA Xilinx FAQs`_
92 The reference design contains one Xilinx UART Lite. This UART is configured as
103 The on-board JTAG is used for configuring and debugging the Xilinx FPGA
114 using Xilinx Vivado as described in the ARM Cortex-M1/Cortex-M3 DesignStart FPGA
115 Xilinx edition user guide (available as part of the reference design download
116 from `Technical Resources for DesignStart FPGA on Xilinx`_).
185 the ARM Cortex-M1/M3 DesignStart FPGA Xilinx edition user guide. If the
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| /Zephyr-Core-3.5.0/boards/arm/zybo/doc/ |
| D | index.rst | 10 circuit development board. It is built around the Xilinx Zynq-7000 family, which is based on the
11 Xilinx All Programmable System-on-Chip (AP SoC) architecture. This architecture tightly integrates a
12 dual-core ARM Cortex-A9 processor with Xilinx 7-series Field Programmable Gate Array (FPGA) logic.
52 achieved in a number of ways (e.g. using the Xilinx First Stage Boot Loader (FSBL), the Xilinx
56 with Xilinx Zynq-7000 series SoCs, see the following documentation:
59 - `Using Distro Boot With Xilinx U-Boot`_
146 .. _Using Distro Boot With Xilinx U-Boot:
147 …https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/749142017/Using+Distro+Boot+With+Xilinx+U-Bo…
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| /Zephyr-Core-3.5.0/drivers/pinctrl/ |
| D | Kconfig.xlnx | 5 bool "Xilinx Zynq 7000 processor system MIO pin controller driver"
10 Enable the Xilinx Zynq 7000 processor system MIO pin controller driver.
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| /Zephyr-Core-3.5.0/soc/arm/xilinx_zynq7000/xc7zxxx/ |
| D | Kconfig.series | 7 bool "Xilinx Zynq-7000 (XC7Zxxx) SoC series"
13 Enable support for the Xilinx Zynq-7000 (XC7Zxxx)
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| /Zephyr-Core-3.5.0/soc/arm/xilinx_zynq7000/xc7zxxxs/ |
| D | Kconfig.series | 7 bool "Xilinx Zynq-7000S (XC7ZxxxS) SoC series"
13 Enable support for the Xilinx Zynq-7000S (XC7ZxxxS)
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| /Zephyr-Core-3.5.0/dts/bindings/spi/ |
| D | xlnx,xps-spi-2.00.a.yaml | 4 description: Xilinx AXI Quad SPI IP node
11 # https://github.com/Xilinx/device-tree-xlnx
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| /Zephyr-Core-3.5.0/include/zephyr/dt-bindings/pinctrl/ |
| D | pinctrl-zynq.h | 13 * Definitions for Xilinx Zynq-7000 pinctrl `power-source` devicetree property values. The value
27 * Definitions for Xilinx Zynq-7000 pinctrl `slew-rate` devicetree property values. The value
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| /Zephyr-Core-3.5.0/drivers/ipm/ |
| D | Kconfig | 51 bool "AMD-Xilinx IPM driver"
55 Inter Processor Interrupt driver for AMD-Xilinx
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| /Zephyr-Core-3.5.0/boards/arm/qemu_cortex_r5/doc/ |
| D | index.rst | 9 This board configuration will use QEMU to emulate the Xilinx Zynq UltraScale+
15 * Xilinx Zynq TTC (Cadence TTC)
16 * Xilinx Zynq UART
61 * Xilinx Zynq TTC driver does not support tickless mode operation.
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| /Zephyr-Core-3.5.0/dts/bindings/gpio/ |
| D | xlnx,ps-gpio.yaml | 7 Xilinx Zynq-7000/ZynqMP MIO/EMIO GPIO controller node.
9 This GPIO controller is contained in both the Xilinx Zynq-7000 and
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| D | xlnx,xps-gpio-1.00.a.yaml | 1 description: Xilinx AXI GPIO IP node
10 # https://github.com/Xilinx/device-tree-xlnx
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