Searched full:usic0 (Results 1 – 3 of 3) sorted by relevance
| /Zephyr-Core-3.5.0/dts/bindings/serial/ |
| D | infineon,xmc4xxx-uart.yaml | 36 Each USIC0..2 has a fifo that is shared between two channels. For example,
81 USIC0..2 have their own interrupt range as follows:
82 USIC0 = [84, 89]
102 simple mapping: in USIC0 interrupt 84->SR0, interrupt 85->SR1, ... etc.
107 For example, say we select interrupt 85 on USIC0, dma0, channel 3, priority 4, and line 7.
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| /Zephyr-Core-3.5.0/dts/bindings/spi/ |
| D | infineon,xmc4xxx-spi.yaml | 37 USIC0 = [84, 89]
57 simple mapping: in USIC0 interrupt 84->SR0, interrupt 85->SR1, ... etc.
62 For example, say we select interrupt 85 on USIC0, dma0, channel 3, priority 4, and line 7.
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| /Zephyr-Core-3.5.0/dts/bindings/i2c/ |
| D | infineon,xmc4xxx-i2c.yaml | 96 USIC0 = [84, 89]
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