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15 * Register address offsets: comp. Zynq-7000 TRM, ug585, chap. B.19
18 /* MIO_PIN_xx SLCR register fields (from Xilinx UG585 v1.13, B.28 SLCR) */52 /* MIO pin function multiplexing (from Xilinx UG585 v1.13, B.28 SLCR) */86 /* MIO SDIO CD/WP pin selection (from Xilinx UG585 v1.13, B.28 SLCR) */163 /* MIO pin groups (from Xilinx UG585 v1.13, table 2-4 "MIO-at-a-Glance") */
45 See the Xilinx Zynq-7000 SoC Technical Reference Manual (UG585) for further details on pin
42 * Comp. Xilinx Zynq-7000 Technical Reference Manual (ug585), chap. B.33
