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/Zephyr-latest/soc/telink/tlsr/tlsr951x/
Dstart.S47 la t2, _AES_DATA_VMA_START
50 bleu t3, t2, _RETENTION_DATA_INIT
51 sw t0, 0(t2)
52 addi t2, t2, 4
57 la t2, _RETENTION_DATA_VMA_START
60 bleu t3, t2, _RAMCODE_INIT
62 sw t0, 0(t2)
64 addi t2, t2, 4
69 la t2, _RAMCODE_VMA_START
72 bleu t3, t2, _START
[all …]
/Zephyr-latest/soc/openisa/rv32m1/
Dwdog.S48 li t2, WDOG_CNT_UNLOCK
49 sw t2, WDOG_CNT_OFFSET(t1)
52 lw t2, WDOG_CS_OFFSET(t1)
53 andi t2, t2, WDOG_CS_EN_DISABLED
54 ori t2, t2, WDOG_CS_UPDATE_ENABLED
55 sw t2, WDOG_CS_OFFSET(t1)
58 li t2, WDOG_TOVAL_SET
59 sw t2, WDOG_TOVAL_OFFSET(t1)
Dsoc_irq.S54 csrr t2, RI5CY_LPCOUNT0
57 sw t2, __soc_esf_t_lpcount0_OFFSET(a0)
60 csrr t2, RI5CY_LPCOUNT1
63 sw t2, __soc_esf_t_lpcount1_OFFSET(a0)
72 lw t2, __soc_esf_t_lpcount0_OFFSET(a0)
75 csrw RI5CY_LPCOUNT0, t2
78 lw t2, __soc_esf_t_lpcount1_OFFSET(a0)
81 csrw RI5CY_LPCOUNT1, t2
/Zephyr-latest/samples/kernel/metairq_dispatch/
DREADME.rst88 (intended) for non-cooperative threads like T2 and T3 which is attributed to delays
118 I: M1 T2 mirq 4273 disp 12740821 proc 40449 real 41710
119 I: M2 T2 mirq 4273 disp 13311098 proc 43926 real 44140
120 I: M3 T2 mirq 4273 disp 13824365 proc 41212 real 41710
121 I: M4 T2 mirq 4273 disp 14382522 proc 12859 real 13765
122 I: M5 T2 mirq 4273 disp 14869754 proc 17303 real 18625
123 I: M7 T2 mirq 4273 disp 15368993 proc 10666 real 11335
124 I: M15 T2 mirq 4273 disp 15364239 proc 45304 real 46570
125 I: M24 T2 mirq 4273 disp 15602017 proc 39637 real 40495
126 I: M28 T2 mirq 4273 disp 15989555 proc 24436 real 24700
[all …]
/Zephyr-latest/tests/net/trickle/src/
Dmain.c63 static struct net_trickle t2; variable
92 ret = net_trickle_create(&t2, T2_IMIN, T2_IMAX, T2_K); in test_trickle_create()
106 ret = net_trickle_start(&t2, cb_2, &t2); in test_trickle_start()
115 zassert_false(net_trickle_stop(&t2), in test_trickle_stop()
132 zassert_true(net_trickle_is_running(&t2), "Trickle 2 not running"); in test_trickle_2_status()
135 net_trickle_consistency(&t2); in test_trickle_2_status()
137 net_trickle_inconsistency(&t2); in test_trickle_2_status()
174 zassert_true(net_trickle_is_running(&t2), "Trickle 2 not running"); in test_trickle_2_wait()
184 zassert_true(net_trickle_is_running(&t2), "Trickle 2 is not running"); in test_trickle_2_inc()
/Zephyr-latest/arch/riscv/core/
Disr.S29 RV_E( op t2, __struct_arch_esf_t2_OFFSET(sp) );\
206 csrr t2, mstatus
207 sr t2, __struct_arch_esf_mstatus_OFFSET(sp)
212 and t1, t1, t2
215 csrr t2, mcause
217 and t2, t2, t1
219 bne t1, t2, no_fp
221 csrr t2, mtval /* get faulting instruction */
227 bnez t2, 1f
228 lw t2, 0(t0) /* t0 = mepc */
[all …]
Dcoredump.c24 uint64_t t2; member
45 uint32_t t2;
94 arch_blk.r.t2 = esf->t2; in arch_coredump_info_dump()
Dreset.S70 li t2, 0xaaaaaaaa
72 sw t2, 0x00(t0)
/Zephyr-latest/soc/neorv32/
Dsoc_irq.S23 csrrc t2, mie, t0
24 and t1, t2, t0
25 csrrs t2, mie, t1
/Zephyr-latest/dts/bindings/led_strip/
Dworldsemi,ws2812-rpi_pico-pio.yaml18 The T2 is equal to T1L in the datasheet.
24 | T0 | T1+T2 |
31 | T0+T1 | T2 |
37 The T0～T2 means ratio in one period.
39 For example, T0=3, T1=3, T2=4 and the frequency is 800kHz case,
/Zephyr-latest/tests/kernel/ipi_cascade/src/
Dmain.c15 * Thread T2 starts on core Y (but is not pinned) at a low priority.
20 * T2 unpends both T3 and T4 and generates an IPI.
90 * Should the threads not be scheduled as expected, abort threads T2,
136 * It is expected to execute on the same CPU that T2 did. in thread4_entry()
151 /* T2 executes at PRIORITY_LOW */
156 /* 5. Indicate T2 is ready. Allow T1 to proceed. */ in thread2_entry()
170 zassert_false(cpu_t2 == cpu_t1, "T2 and T1 unexpectedly on the same CPU"); in thread2_entry()
174 * will result in executing T4 on T2's CPU. in thread2_entry()
213 /* 4. Create T2 and spin until it is ready. */ in ZTEST()
218 k_thread_name_set(&thread2, "T2"); in ZTEST()
[all …]
/Zephyr-latest/tests/kernel/mutex/mutex_api/src/
Dtest_mutex_apis.c145 /* wait for t2 timeout to get mutex*/ in tThread_T1_priority_inheritance()
153 /* wait for t2 timeout to get mutex*/ in tThread_T1_priority_inheritance()
169 "access locked resource from spawn thread T2"); in tThread_T2_priority_inheritance()
175 "T2 should not get the resource"); in tThread_T2_priority_inheritance()
312 * - case 1. When priority T2 > T1, priority inheritance happened.
313 * - case 2. When priority T1 > T2, priority inheritance won't happened.
314 * - case 3. When priority T2 > T3 > T1, priority inheritance happened but T2
320 /**TESTPOINT: run test case 1, given priority T1 < T2 */ in ZTEST_USER()
340 /* spawn a higher priority thread t2 for holding the mutex */ in ZTEST_USER()
347 /* wait for spawn thread t2 to take action */ in ZTEST_USER()
[all …]
/Zephyr-latest/arch/mips/core/
Disr.S45 op t2, ESF_O(t2)(sp) ;\
200 OP_LOADREG t2, _kernel_offset_to_current(k1)
207 beq t3, t2, no_reschedule
225 OP_LOADREG t2, _kernel_offset_to_current(t0)
227 beq t2, t3, no_reschedule
248 la t2, _k_neg_eagain
249 lw t3, 0(t2)
275 OP_LOADREG t2, ESF_O(lo)(sp)
277 mtlo t2
Dreset.S39 li t2, 0xaaaaaaaa
41 sw t2, 0(t0)
Dfatal.c20 LOG_ERR("$ 8 : %08lx(t0) %08lx(t1) %08lx(t2) %08lx(t3)\n", in z_mips_fatal_error()
21 esf->t0, esf->t1, esf->t2, esf->t3); in z_mips_fatal_error()
/Zephyr-latest/scripts/coccinelle/
Dboolean.cocci17 type T1, T2;
22 T1 function(P1, T2 v, P2) {...}
24 T1 function(P1, T2 *v, P2) {...}
28 t << rule1_base.T2;
Dsame_identifier.cocci58 type T1, T2;
64 T1 function(P1, T2 *v@p, P2) {
70 t << function_match.T2;
Dreserved_names.cocci73 type T1, T2;
79 T1 function(P1, T2 *v@p, P2) {
/Zephyr-latest/soc/nordic/common/vpr/
Dsoc_isr_stacking.h26 unsigned long t2; \
50 unsigned long t2; \
102 or t2, t1, t0; \
103 sr t2, __struct_arch_esf_mepc_OFFSET(sp)
/Zephyr-latest/samples/boards/nordic/coresight_stm/src/
Dmain.c61 uint32_t t0, t1, t2, t3, t_s; in main() local
75 t2 = TEST_LOG(rpt, (LOG_INF("test with two arguments %d %d", 100, 10))); in main()
76 t2 -= delta; in main()
97 timing_report(t2, rpt, "log message with 2 arguments"); in main()
/Zephyr-latest/subsys/net/lib/dhcpv6/
Ddhcpv6.c74 uint32_t t1, uint32_t t2, in dhcvp6_update_deadlines() argument
80 /* In case server does not set T1/T2 values, the time choice is left to in dhcvp6_update_deadlines()
83 * set T1/T2 as 0.5 and 0.8 of the preferred lifetime. in dhcvp6_update_deadlines()
85 if (t1 == 0 && t2 == 0) { in dhcvp6_update_deadlines()
88 t2 = DHCPV6_INFINITY; in dhcvp6_update_deadlines()
91 t2 = preferred_lifetime * 0.8; in dhcvp6_update_deadlines()
94 if (t2 == DHCPV6_INFINITY) { in dhcvp6_update_deadlines()
97 t1 = t2 * 0.625; /* 0.5 / 0.8 */ in dhcvp6_update_deadlines()
99 } else if (t2 == 0) { in dhcvp6_update_deadlines()
101 t2 = DHCPV6_INFINITY; in dhcvp6_update_deadlines()
[all …]
/Zephyr-latest/drivers/led_strip/
Dws2812_rpi_pico_pio.c209 * This pio program runs [T0+T1+T2] cycles per 1 loop.
210 * The first `out` instruction outputs 0 by [T2] times to the sideset pin.
218 * After output, return to the first line and output 0 by [T2] times.
220 * In the case of configuration, T0=3, T1=3, T2 =4,
231 SET_DELAY(0x6021, inst, 2), /* 0: out x, 1 side 0 [T2 - 1] */ \
/Zephyr-latest/tests/arch/riscv/fatal/
Dtestcase.yaml17 - "E: a2: a2ff0000ff000c12 t2: d2ff0000ff000707"
/Zephyr-latest/doc/develop/west/
Dworkspaces.rst157 - T2: star topology, a Zephyr application is the manifest repository
171 .. _west-t2:
173 T2: Star topology, application is the manifest repository
211 # Example T2 west.yml, using manifest imports.
323 as shown :ref:`above <west-t2>` for the T2 topology, with the same caveats.
/Zephyr-latest/scripts/coredump/gdbstubs/arch/
Drisc_v.py24 T2 = 7 variable in RegNum
82 self.registers[RegNum.T2] = tu[4]

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