1# Copyright (c) 2019 Foundries.io
2# Copyright (C) 2019 Peter Bigot Consulting, LLC
3# Copyright (C) 2021 Peter Johanson
4# SPDX-License-Identifier: Apache-2.0
5
6description: |
7    GPIO pins exposed on Seeeduino Xiao (and compatible devices) headers.
8
9    The Seeeeduino Xiao layout provides two headers, along opposite
10    edges of the board.
11
12    Proceeding counter-clockwise:
13    * A 7-pin Digital/Analog Input header.  This has input signals
14      labeled from 0 at the top through 6 at the bottom.
15    * An 7-pin header Power and Digital/Analog Input header.  This
16      has three power pins, followed by four inputs labeled 10 at the
17      top through 7 at the bottom.
18
19    This binding provides a nexus mapping for 10 pins where parent pins 0
20    through 10 correspond to D0 through D10, as depicted below:
21
22        0 D0                     5V   -
23        1 D1                     GND  -
24        2 D2                     3V3  -
25        3 D3                     D10 10
26        4 A4                     D9   9
27        5 D5                     D8   8
28        6 D6                     D7   7
29
30
31compatible: "seeed,xiao-gpio"
32
33include: [gpio-nexus.yaml, base.yaml]
34