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/Zephyr-latest/scripts/native_simulator/common/src/include/
Dnsi_cpu_if.h18 * embedded SW library, both by the native simulator runner,
19 * and other possible embedded CPU's SW.
29 * The interface between the embedded SW and the native simulator is allocated in its
32 * It is also be possible for the embedded SW to require the linker to keep those
35 * It is also possible for the embedded SW developers to not use garbage collection
36 * during their SW linking.
47 * The embedded SW library may provide this function to perform any
56 * The embedded SW library may provide this function to perform any
64 * The embedded SW library must provide this function.
68 * The expectation is that the embedded CPU SW will spawn a
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/Zephyr-latest/soc/openisa/rv32m1/
Dsoc_irq.S36 sw t1, 0x00(t0)
55 sw t0, __soc_esf_t_lpstart0_OFFSET(a0)
56 sw t1, __soc_esf_t_lpend0_OFFSET(a0)
57 sw t2, __soc_esf_t_lpcount0_OFFSET(a0)
61 sw t0, __soc_esf_t_lpstart1_OFFSET(a0)
62 sw t1, __soc_esf_t_lpend1_OFFSET(a0)
63 sw t2, __soc_esf_t_lpcount1_OFFSET(a0)
Dwdog.S49 sw t2, WDOG_CNT_OFFSET(t1)
55 sw t2, WDOG_CS_OFFSET(t1)
59 sw t2, WDOG_TOVAL_OFFSET(t1)
/Zephyr-latest/snippets/bt-ll-sw-split/
Dsnippet.yml1 name: bt-ll-sw-split
3 EXTRA_CONF_FILE: bt-ll-sw-split.conf
4 EXTRA_DTC_OVERLAY_FILE: bt-ll-sw-split.overlay
DREADME.rst1 .. _snippet-bt-ll-sw-split:
3 Zephyr Bluetooth LE Controller (bt-ll-sw-split)
11 west build -S bt-ll-sw-split [...]
/Zephyr-latest/scripts/native_simulator/common/src/
Dnce.c11 * the hosted embedded OS / SW can use to emulate the CPU
15 * and SW operation, so that only one of them executes at
77 * If called from a SW thread, release the HW thread which is blocked in
117 /* This SW thread will wait until being cancelled from in nce_terminate()
130 * Both HW and SW threads will use this function to transfer control to the
167 * Helper function that wraps the SW start_routine
180 NCE_DEBUG("SW init started (%lu)\n", in sw_wrapper()
190 * * Spawn a new pthread which will run the first embedded SW thread <start_routine>
191 * * Hold the caller until that embedded SW thread (or a child it spawns)
194 * Note that during this, an embedded SW thread may call nsi_exit(), which would result
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/Zephyr-latest/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/
Dradio_nrf5_ppi_resources.h93 /* PPI setup used for SW-based auto-switching during TIFS. */
97 /* Clear SW-switch timer on packet end:
106 /* Clear event timer (sw-switch timer) on Radio end:
117 /* Wire a SW SWITCH TIMER EVENTS_COMPARE[<cc_offset>] event
138 * wire the SW SWITCH TIMER EVENTS_COMPARE[<cc_offset>] event
152 /* Wire the SW SWITCH TIMER EVENTS_COMPARE[<cc_offset>] event
157 /* Cancel the SW switch timer running considering S8 timing:
165 /* Wire the SW SWITCH PHYEND delay compensation TIMER EVENTS_COMPARE[<cc_offset>] event to software
173 /* Cancel the SW switch timer running considering PHYEND delay compensation timing:
Dradio_nrf5_dppi_resources.h92 /* DPPI setup used for SW-based auto-switching during TIFS. */
94 /* Clear SW-switch timer on packet end:
108 /* Wire a SW SWITCH TIMER EVENTS_COMPARE[<cc_offset>] event
115 /* Enable the SW Switch PPI Group on RADIO END Event.
122 /* Enable Radio on SW Switch timer event.
123 * Wire a SW SWITCH TIMER EVENTS_COMPARE[<cc_offset>] event
127 * We use the same PPI as for disabling the SW Switch PPI groups,
128 * since we need to listen for the same event (SW Switch event).
130 * We use the same PPI for the alternative SW Switch Timer compare
141 /* Cancel the SW switch timer running considering S8 timing:
[all …]
Dradio_nrf5_dppi.h227 /* DPPI setup used for SW-based auto-switching during TIFS. */
229 /* Clear SW-switch timer on packet end:
283 /* Wire a SW SWITCH TIMER EVENTS_COMPARE[<cc_offset>] event
303 /* Enable the SW Switch PPI Group on RADIO END Event.
316 /* Enable Radio on SW Switch timer event.
317 * Wire a SW SWITCH TIMER EVENTS_COMPARE[<cc_offset>] event
321 * We use the same PPI as for disabling the SW Switch PPI groups,
322 * since we need to listen for the same event (SW Switch event).
324 * We use the same PPI for the alternative SW Switch Timer compare
341 /* Cancel the SW switch timer running considering S8 timing:
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/Zephyr-latest/soc/st/stm32/stm32wbax/hci_if/
Dlinklayer_plat_adapt.c33 /* Radio SW low ISR global variable */
81 /* Check if nested SW radio low interrupt has been requested*/ in radio_low_prio_isr()
87 /* Re-enable SW radio low interrupt */ in radio_low_prio_isr()
124 /* Check if a SW low interrupt as already been raised. in LINKLAYER_PLAT_TriggerSwLowIT()
129 /* No nested SW low ISR, default behavior */ in LINKLAYER_PLAT_TriggerSwLowIT()
138 /* No change for SW radio low interrupt priority for the moment */ in LINKLAYER_PLAT_TriggerSwLowIT()
141 /* At the end of current SW radio low ISR, this pending SW in LINKLAYER_PLAT_TriggerSwLowIT()
/Zephyr-latest/drivers/mbox/
DKconfig.andes9 bool "MBOX Andes PLIC-SW driver"
15 Enable the driver for the Andes PLIC-SW based MBOX controller.
/Zephyr-latest/dts/bindings/mbox/
Dandestech,mbox-plic-sw.yaml8 This is a representation of AndesTech MBOX PLIC-SW node
10 compatible: "andestech,mbox-plic-sw"
/Zephyr-latest/modules/lvgl/
DCMakeLists.txt89 ${LVGL_DIR}/src/draw/sw/blend/lv_draw_sw_blend.c
90 ${LVGL_DIR}/src/draw/sw/blend/lv_draw_sw_blend_to_al88.c
91 ${LVGL_DIR}/src/draw/sw/blend/lv_draw_sw_blend_to_argb8888.c
92 ${LVGL_DIR}/src/draw/sw/blend/lv_draw_sw_blend_to_i1.c
93 ${LVGL_DIR}/src/draw/sw/blend/lv_draw_sw_blend_to_l8.c
94 ${LVGL_DIR}/src/draw/sw/blend/lv_draw_sw_blend_to_rgb565.c
95 ${LVGL_DIR}/src/draw/sw/blend/lv_draw_sw_blend_to_rgb888.c
96 ${LVGL_DIR}/src/draw/sw/lv_draw_sw_arc.c
97 ${LVGL_DIR}/src/draw/sw/lv_draw_sw_border.c
98 ${LVGL_DIR}/src/draw/sw/lv_draw_sw_box_shadow.c
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/Zephyr-latest/soc/telink/tlsr/tlsr951x/
Dstart.S51 sw t0, 0(t2)
62 sw t0, 0(t2)
74 sw t0, 0(t2)
Dsoc_irq.S32 sw t0, __soc_esf_t_mxstatus_OFFSET(a0)
35 sw t1, __soc_esf_t_ucode_OFFSET(a0)
/Zephyr-latest/dts/bindings/pinctrl/
Dst,stm32f1-pinctrl.yaml31 * full - Full SWJ (JTAG-DP + SW-DP).
32 * no-njtrst - Full SWJ (JTAG-DP + SW-DP) but without NJTRST.
34 * jtag-disable - JTAG-DP Disabled and SW-DP Enabled.
36 * disable - JTAG-DP Disabled and SW-DP Disabled.
39 If absent, then Full SWJ (JTAG-DP + SW-DP) is used (reset state).
/Zephyr-latest/dts/bindings/pwm/
Dnordic,nrf-sw-pwm.yaml3 compatible: "nordic,nrf-sw-pwm"
36 sw_pwm: sw-pwm {
37 compatible = "nordic,nrf-sw-pwm";
/Zephyr-latest/drivers/watchdog/
DKconfig.smartbond26 Note that this bit can only be set to 1 by SW and
27 only be reset with a WDOG (SYS) reset or SW reset.
/Zephyr-latest/soc/andestech/ae350/
Dsoc_irq.S28 sw t0, __soc_esf_t_mxstatus_OFFSET(a0)
31 sw t1, __soc_esf_t_ucode_OFFSET(a0)
/Zephyr-latest/boards/native/nrf_bsim/common/
Dbstests.h24 * This is BEFORE any SW has run, and before the HW has been initialized
50 * It will be called (in SW context) when a HW interrupt is raised.
58 * This function will be called (in SW context) as a Zephyr PRE_KERNEL_1
66 * This function will be called (in SW context) as a Zephyr POST_KERNEL
73 * This function will be called (in SW context) as the Zephyr application main
/Zephyr-latest/subsys/bluetooth/controller/ll_sw/openisa/hal/RV32M1/
Dswi.h16 /* SW IRQs required for the SW defined BLE Controller on RV32M1. */
/Zephyr-latest/boards/native/native_posix/
Dirq_handler.c7 * SW side of the IRQ handling
116 * will interrupt the SW itself
117 * (this function should only be called from the HW model code, from SW threads)
223 * @param flags [plug it directly (1), or as a SW managed interrupt (0)]
256 * set a pending IRQ from SW
269 * clear a pending irq from SW
284 * IRQ handler for the SW interrupt assigned to irq_offload()
295 * Raise the SW IRQ assigned to handled this
/Zephyr-latest/boards/native/native_sim/
Dirq_handler.c8 * SW side of the IRQ handling
124 * will interrupt the SW itself
125 * (this function should only be called from the HW model code, from SW threads)
231 * @param flags [plug it directly (1), or as a SW managed interrupt (0)]
264 * set a pending IRQ from SW
277 * clear a pending irq from SW
292 * IRQ handler for the SW interrupt assigned to irq_offload()
303 * Raise the SW IRQ assigned to handled this
/Zephyr-latest/boards/native/nrf_bsim/
Dirq_handler.c6 * SW side of the IRQ handling
146 * will interrupt the SW itself
147 * (this function should only be called from the HW model code, from SW threads)
253 * @param flags [plug it directly (1), or as a SW managed interrupt (0)]
286 * set a pending IRQ from SW
299 * clear a pending irq from SW
314 * IRQ handler for the SW interrupt assigned to irq_offload()
325 * Raise the SW IRQ assigned to handled this
/Zephyr-latest/arch/riscv/core/
Duserspace.S29 sw a5, 0(a2) # Init error value to 0
50 sw a4, 0(a2)

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