Searched full:slcr (Results 1 – 8 of 8) sorted by relevance
| /Zephyr-latest/drivers/pinctrl/ |
| D | pinctrl_xlnx_zynq.c | 20 /* Relative SLCR register offsets for use in asserts */
25 static const struct device *const slcr = DEVICE_DT_GET(DT_INST_PHANDLE(0, syscon)); variable
38 if (!device_is_ready(slcr)) { in pinctrl_configure_pins()
39 LOG_ERR("SLCR device not ready"); in pinctrl_configure_pins()
53 err = syscon_read_reg(slcr, addr, &val); in pinctrl_configure_pins()
55 LOG_ERR("failed to read SLCR addr 0x%04x (err %d)", addr, err); in pinctrl_configure_pins()
67 err = syscon_write_reg(slcr, addr, val); in pinctrl_configure_pins()
69 LOG_ERR("failed to write SLCR addr 0x%04x (err %d)", addr, err); in pinctrl_configure_pins()
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| /Zephyr-latest/dts/bindings/pinctrl/ |
| D | xlnx,pinctrl-zynq.yaml | 56 Base address and size of the System Level Control Registers (SLCR) space.
62 phandle to the System Level Control Registers (SLCR).
144 L3_SEL, L2_SEL, L1_SEL, and L0_SEL fields in the MIO_PIN_xx SLCR register.
149 SLCR register.
153 Enables tri-state on IO buffer pin. Sets the TRI_ENABLE field in the MIO_PIN_xx SLCR
158 Enables pull-up on IO buffer pin. Sets the PULLUP field in the MIO_PIN_xx SLCR register.
163 power-source (IO_Type) is HSTL. Sets the DisableRcvr field in the MIO_PIN_xx SLCR
169 DisableRcvr field in the MIO_PIN_xx SLCR register.
174 IO buffer type. Sets the IO_Type field in the MIO_PIN_xx SLCR register. The IO_STANDARD_*
186 LVCMOS33. Sets the Speed field in the MIO_PIN_xx SLCR register. The IO_SPEED_* macros are
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| /Zephyr-latest/include/zephyr/dt-bindings/pinctrl/ |
| D | pinctrl-zynq.h | 14 * corresponds to what is written to the IO_Type field in the MIO_PIN_xx SLCR register.
28 * corresponds to what is written to the Speed field in the MIO_PIN_xx SLCR register.
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| /Zephyr-latest/soc/xlnx/zynq7000/xc7zxxx/ |
| D | soc.c | 16 /* System Level Control Registers (SLCR) */
101 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(slcr)) in soc_reset_hook()
102 mm_reg_t addr = DT_REG_ADDR(DT_NODELABEL(slcr)); in soc_reset_hook()
104 /* Unlock System Level Control Registers (SLCR) */ in soc_reset_hook()
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| /Zephyr-latest/soc/xlnx/zynq7000/xc7zxxxs/ |
| D | soc.c | 101 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(slcr)) in soc_reset_hook()
102 mm_reg_t addr = DT_REG_ADDR(DT_NODELABEL(slcr)); in soc_reset_hook()
104 /* Unlock System Level Control Registers (SLCR) */ in soc_reset_hook()
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| /Zephyr-latest/dts/arm/xilinx/ |
| D | zynq7000.dtsi | 172 slcr: slcr@f8000000 { label
175 compatible = "xlnx,zynq-slcr", "syscon";
182 syscon = <&slcr>;
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| /Zephyr-latest/soc/xlnx/zynq7000/common/ |
| D | pinctrl_soc.h | 18 /* MIO_PIN_xx SLCR register fields (from Xilinx UG585 v1.13, B.28 SLCR) */
46 /* MIO_PIN_xx SLCR register L3..L0 multiplexing fields combined */
52 /* MIO pin function multiplexing (from Xilinx UG585 v1.13, B.28 SLCR) */
86 /* MIO SDIO CD/WP pin selection (from Xilinx UG585 v1.13, B.28 SLCR) */
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| /Zephyr-latest/drivers/ethernet/ |
| D | eth_xlnx_gem_priv.h | 118 * GEMx_CLK_CTRL (SLCR) registers:
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