| /Zephyr-latest/soc/snps/arc_iot/ |
| D | sysconf.h | 33 volatile uint32_t I2S_TX_SCLKDIV; /* I2S TX SCLK divisor */
34 volatile uint32_t I2S_RX_SCLKDIV; /* I2S RX SCLK divisor */
35 volatile uint32_t I2S_RX_SCLKSEL; /* I2S RX SCLK source select */
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| /Zephyr-latest/drivers/adc/ |
| D | adc_ads7052.c | 196 * after the first SCLK falling edge. Subsequent output bits are launched on the subsequent rising
197 * edges provided on SCLK. When all 14 output bits are shifted out, the device outputs 0's on the
198 * subsequent SCLK rising edges. The device enters the ACQ state after 18 clocks and a minimum time
200 * 18 SCLK falling edges in the present serial transfer frame, the device provides an invalid
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| /Zephyr-latest/dts/bindings/gpio/ |
| D | st,dsi-lcd-qsh-030.yaml | 26 35 SCLK/MCLK VDD(2.8V-3.3V) (36)
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| /Zephyr-latest/drivers/watchdog/ |
| D | wdt_sam.c | 67 int wdt_sam_convert_timeout(uint32_t timeout, uint32_t sclk) in wdt_sam_convert_timeout() argument
72 min = (SAM_PRESCALAR * 1000000) / sclk; in wdt_sam_convert_timeout()
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| /Zephyr-latest/boards/st/stm32h747i_disco/ |
| D | stm32h747i_disco.dtsi | 82 <35 0 &gpioe 5 0>, /* SCLK/MCLK */
|
| /Zephyr-latest/boards/nxp/rd_rw612_bga/dts/ |
| D | goworld_16880_lcm.overlay | 36 * 5 | SCLK | J5.6 (LCD_SPI_SCK)
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| /Zephyr-latest/soc/altr/zephyr_nios2f/cpu/ |
| D | ghrd_10m50da_top.v | 95 … (spi_sclk), // .SCLK
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| /Zephyr-latest/samples/drivers/led/led_strip/ |
| D | README.rst | 42 #. Connect the SCLK pin of your board's SPI master to the clock input
|
| /Zephyr-latest/boards/shields/tcan4550evm/doc/ |
| D | index.rst | 50 | D13 | SCLK |
|
| /Zephyr-latest/boards/shields/ls0xx_generic/doc/ |
| D | index.rst | 46 | SCLK | Serial Clock Input |
|
| /Zephyr-latest/drivers/i2c/ |
| D | i2c_esp32.c | 270 i2c_clock_source_t sclk = i2c_get_clk_src(bitrate); in i2c_esp32_configure_bitrate() local
271 uint32_t clk_freq_mhz = i2c_get_src_clk_freq(sclk); in i2c_esp32_configure_bitrate()
273 i2c_hal_set_bus_timing(&data->hal, bitrate, sclk, clk_freq_mhz); in i2c_esp32_configure_bitrate()
|
| /Zephyr-latest/boards/atmel/sam0/samr21_xpro/doc/ |
| D | index.rst | 143 | SCLK | PC18 (OUT, SPI SCLK) …
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| /Zephyr-latest/boards/st/stm32u5a9j_dk/ |
| D | stm32u5a9j_dk.dts | 55 <35 0 &gpioe 5 0>, /* SCLK/MCLK */
|
| /Zephyr-latest/boards/atmel/sam0/samr21_xpro/ |
| D | samr21_xpro.dts | 151 * CS-PB31; MOSI-PB30; MISO-PC19; SCLK-PC18
|
| /Zephyr-latest/boards/shields/atmel_rf2xx/doc/ |
| D | index.rst | 62 | 8 | SCLK | SPI Clock |
119 | 18 | SCLK | SPI Clock |
166 | D13 | SCLK | SPI Clock |
197 | SCK | SCLK | SPI Clock |
|
| /Zephyr-latest/boards/shields/ftdi_vm800c/doc/ |
| D | index.rst | 48 | D13 | SCLK | SPI Clock |
|
| /Zephyr-latest/drivers/dai/intel/ssp/ |
| D | dai-params-intel-ipc4.h | 287 /* specifies if parameters target MCLK (1) or SCLK (0) */
|
| /Zephyr-latest/drivers/sdhc/ |
| D | sdhc_spi.c | 362 * The SD card can take up to 8 bytes worth of SCLK cycles to respond. in sdhc_spi_send_cmd()
387 /* We cannot send extra SCLK cycles with our command, in sdhc_spi_send_cmd()
741 LOG_ERR("Card SCLK init sequence failed"); in sdhc_spi_set_io()
|
| /Zephyr-latest/drivers/flash/ |
| D | flash_mcux_flexspi_hyperflash.c | 436 /* Clock FlexSPI at 84 MHZ (42MHz SCLK in DDR mode) */ in flash_flexspi_hyperflash_write()
481 /* Clock FlexSPI at 332 MHZ (166 MHz SCLK in DDR mode) */ in flash_flexspi_hyperflash_write()
|
| /Zephyr-latest/boards/adafruit/feather_m4_express/doc/ |
| D | index.rst | 87 into SPI mode and used to connect to devices over the SCK (SCLK), MO (MOSI), and
|
| /Zephyr-latest/boards/adafruit/itsybitsy_m4_express/doc/ |
| D | index.rst | 88 into SPI mode and used to connect to devices over the SCK (SCLK), MO (MOSI), and
|
| /Zephyr-latest/boards/silabs/radio_boards/slwrb4104a/doc/ |
| D | index.rst | 96 | PC8 | SPI_SCLK | Flash SCLK US1_CLK #11 |
|
| /Zephyr-latest/boards/silabs/radio_boards/slwrb4161a/doc/ |
| D | index.rst | 90 | PC8 | SPI_SCLK | Flash SCLK US1_CLK #11 |
|
| /Zephyr-latest/boards/silabs/radio_boards/slwrb4170a/doc/ |
| D | index.rst | 90 | PC8 | SPI_SCLK | Flash SCLK US1_CLK #11 |
|
| /Zephyr-latest/boards/silabs/radio_boards/slwrb4250b/doc/ |
| D | index.rst | 94 | PC8 | SPI_SCLK | Flash SCLK US1_CLK #11 |
|
