| /Zephyr-Core-2.7.6/tests/drivers/hwinfo/api/src/ |
| D | main.c | 75 * @brief TestPurpose: verify get reset cause works.
79 * -# Read the reset cause
104 zassert_not_equal(cause, 0xDEADBEEF, "Reset cause not written."); in test_get_reset_cause()
111 * @brief TestPurpose: verify clear reset cause works. This may
112 * not work on some platforms, depending on how reset cause register
116 * -# Read the reset cause and store the result
117 * -# Call clear reset cause
118 * -# Read the reset cause again
121 * -# Reset cause value should change after calling clear reset cause.
158 "Reset cause did not change after clearing"); in test_clear_reset_cause()
[all …]
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| /Zephyr-Core-2.7.6/boards/arm/stm32f746g_disco/support/ |
| D | openocd.cfg | 5 reset halt
14 # Event reset-init already uses the maximum speed however adapter speed
15 # inherited from stm32f7x.cfg for reset-start defaults to 2000 kHz, so
17 $_TARGETNAME configure -event reset-start {
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| /Zephyr-Core-2.7.6/arch/nios2/core/ |
| D | crt0.S | 26 * Reset vector entry point into the system. Placed into special 'reset'
31 * is usually configured to be 0x20 past the reset vector.
33 SECTION_FUNC(reset, __reset)
36 /* Aside from the instruction cache line associated with the reset
38 * reset. To ensure cache coherency after reset, the reset handler
39 * located at the reset vector must immediately initialize the
40 * instruction cache. Next, either the reset handler or a subsequent
79 * we're not booting from our reset vector, either by a bootloader
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| /Zephyr-Core-2.7.6/dts/bindings/mtd/ |
| D | nxp,imx-flexspi-device.yaml | 21 default corresponds to the reset value of the register field.
30 default corresponds to the reset value of the register field.
39 reset value of the register field.
48 reset value of the register field.
65 FLASHB2CR0. The default corresponds to the reset value of the register
92 corresponds to the reset value of the register field.
101 corresponds to the reset value of the register field.
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| /Zephyr-Core-2.7.6/include/drivers/ |
| D | hwinfo.h | 71 * @brief Retrieve cause of device reset.
75 * This routine retrieves the flags that indicate why the device was reset.
77 * On some platforms the reset cause flags accumulate between successive resets
78 * and this routine may return multiple flags indicating all reset causes
80 * the most recent reset call `hwinfo_clear_reset_cause` after calling this
81 * routine to clear the hardware flags before the next reset event.
95 * @brief Clear cause of device reset.
97 * Clears reset cause flags.
108 * @brief Get supported reset cause flags
|
| /Zephyr-Core-2.7.6/arch/riscv/core/ |
| D | reboot.c | 17 * @brief Reset the system
20 * RISC-V specification does not have a common interface for system reset.
21 * Each RISC-V SoC that has reset feature should implement own reset function.
|
| /Zephyr-Core-2.7.6/boards/arm/b_u585i_iot02a/support/ |
| D | openocd.cfg | 19 # Reset configuration
20 # use hardware reset, connect under reset
37 reset halt
|
| /Zephyr-Core-2.7.6/boards/arm/nucleo_u575zi_q/support/ |
| D | openocd.cfg | 19 # Reset configuration
20 # use hardware reset, connect under reset
37 reset halt
|
| /Zephyr-Core-2.7.6/boards/arm/reel_board/support/ |
| D | pyocd.yaml | 3 # Use HW reset option on reel_board
5 # Delay for 0.5s after the reset is issued
6 reset.post_delay: 0.5
|
| /Zephyr-Core-2.7.6/soc/arm/nxp_kinetis/ |
| D | Kconfig | 110 protection settings (loaded on reset) and security information that
124 Configures the reset value of the FSEC register, which includes
133 Configures the reset value of the FOPT register, which includes boot,
141 Configures the reset value of the FEPROT register for FlexNVM
149 Configures the reset value of the FDPROT register for FlexNVM
159 window for configuration upon reset. Therefore, this
160 requires that the watchdog be configured during reset
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| /Zephyr-Core-2.7.6/boards/xtensa/intel_adsp_cavs15/tools/lib/ |
| D | device.py | 151 # Set Reset Bit for cores
152 logging.debug("Enter core reset(mask=0x%08X)" % core_mask)
154 reset = core_mask << regs_def.ADSP_GR_ADSPCS_CRST_OFFSET
155 self._update_bits(self.dsp_ctl_sts, reset, reset)
157 # Check core entered reset
159 if (reg & reset) != reset:
160 raise RuntimeError("Reset enter failed: DSP_CTL_STS=%s core_maks=0x%08X"
165 # Set Reset Bit for cores
166 logging.debug("Leave core reset(mask=0x%08X)" % core_mask)
171 # Check core entered reset
[all …]
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| /Zephyr-Core-2.7.6/boards/arm/nrf9160dk_nrf52840/dts/bindings/ |
| D | nordic,nrf9160dk-nrf52840-reset.yaml | 7 description: GPIO used to reset nRF52840 on nRF9160 DK
9 compatible: "nordic,nrf9160dk-nrf52840-reset"
21 GPIO to use as nRF52840 reset line: output in nRF9160, input in nRF52840.
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| /Zephyr-Core-2.7.6/boards/arm/nrf9160dk_nrf9160/dts/bindings/ |
| D | nordic,nrf9160dk-nrf52840-reset.yaml | 7 description: GPIO used to reset nRF52840 on nRF9160 DK
9 compatible: "nordic,nrf9160dk-nrf52840-reset"
21 GPIO to use as nRF52840 reset line: output in nRF9160, input in nRF52840.
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| /Zephyr-Core-2.7.6/drivers/counter/ |
| D | Kconfig.stm32_rtc | 79 bool "Do backup domain reset"
82 Force a backup domain reset on startup
89 Do not reset the rtc time and date after each reset.
|
| /Zephyr-Core-2.7.6/dts/bindings/ieee802154/ |
| D | nxp,mcr20a.yaml | 20 reset-gpios:
23 description: RESET pin.
25 The RESET pin of MCR20A is active low.
|
| D | decawave,dw1000.yaml | 20 reset-gpios:
23 description: RESET pin.
25 The RESET pin of DW1000 is active low.
|
| /Zephyr-Core-2.7.6/dts/bindings/ethernet/ |
| D | wiznet,w5500.yaml | 19 reset-gpios:
22 description: Reset pin.
24 The reset pin of W5500 is active low.
|
| /Zephyr-Core-2.7.6/soc/arm/microchip_mec/mec172x/reg/ |
| D | mec172x_pcr.h | 58 * RST_EN bit = 1 will reset the peripheral at any time. The RST_EN registers
59 * must be unlocked by writing the unlock code to PCR Peripheral Reset Lock
75 * Write unlock code to PCR Peripheral Reset Lock
77 * Selected peripherals will be reset.
78 * Write lock code to PCR Peripheral Reset Lock.
125 /* PCR Power Reset Status Register */
138 /* PCR Power Reset Control Register */
144 /* PCR System Reset Register */
155 * Reset Enable Reg 0 (Offset +70h)
164 * Reset Enable Reg 1 (Offset +74h)
[all …]
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| /Zephyr-Core-2.7.6/tests/drivers/watchdog/wdt_basic_api/src/ |
| D | test_wdt.c | 12 * and reset can be triggered when timeout
15 * wait for reset. Three variables are placed in noinit section to prevent
16 * clearing them during board reset.These variables save number of the current
25 * -# Wait for reset.
27 * -# If reset comes, the same testcase should be executed but state should
37 * -# Wait for reset.
39 * -# If reset comes, the same testcase should be executed but state should be
41 * right before reset.
51 * -# Wait for reset and feed first watchdog.
53 * -# If reset comes, the same testcase should be executed but state should be
[all …]
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| /Zephyr-Core-2.7.6/doc/reference/peripherals/ |
| D | hwinfo.rst | 10 identifiers and reset cause flags.
12 Reset cause flags can be used to determine why the device was reset; for example
|
| /Zephyr-Core-2.7.6/soc/xtensa/esp32/ |
| D | soc.c | 168 /* Reset them to the defaults expected by ROM */ in esp_restart_noos()
176 /* Reset wifi/bluetooth/ethernet/sdio (bb/mac) */ in esp_restart_noos()
185 /* Reset timer/spi/uart */ in esp_restart_noos()
188 /* UART TX FIFO cannot be reset correctly on ESP32, */ in esp_restart_noos()
189 /* so reset the UART memory by DPORT here. */ in esp_restart_noos()
197 /* Reset CPUs */ in esp_restart_noos()
199 /* Running on PRO CPU: APP CPU is stalled. Can reset both CPUs. */ in esp_restart_noos()
203 /* Running on APP CPU: need to reset PRO CPU and unstall it, */ in esp_restart_noos()
204 /* then reset APP CPU */ in esp_restart_noos()
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| /Zephyr-Core-2.7.6/arch/arc/core/ |
| D | reset.S | 9 * @brief Reset handler
11 * Reset handler that prepares the system for running C code.
35 * @brief Reset vector
37 * Ran when the system comes out of reset. The processor is at supervisor level.
117 * Force to initialize internal architecture state to reset values
120 * substitution of normal hardware reset sequence.
125 /* Set default reset value to _ARC_V2_MPU_EN register */
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| /Zephyr-Core-2.7.6/scripts/west_commands/runners/ |
| D | dfu.py | 37 self.reset = False
96 self.reset = True
97 print('Please reset your board to switch to DFU mode...')
124 # Normal DFU devices generally need to be reset to switch
129 self.reset = False
130 if self.reset:
131 print('Now reset your board again to switch back to runtime mode.')
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| /Zephyr-Core-2.7.6/boards/arm/lora_e5_dev_board/ |
| D | board.cmake | 5 board_runner_args(pyocd "--flash-opt=-O connect_mode=under-reset")
6 board_runner_args(jlink "--device=STM32WLE5JC" "--speed=4000" "--reset-after-load")
7 board_runner_args(stm32cubeprogrammer "--port=swd" "--reset=hw")
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| /Zephyr-Core-2.7.6/include/dt-bindings/clock/ |
| D | esp32_clock.h | 68 #define ESP32_SECUREBOOT_MODULE 35 /* Secure boot reset will hold SHA & AES in reset */
69 …e ESP32_DIGITAL_SIGNATURE_MODULE 36 /* Digital signature reset will hold AES & RSA in reset */
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