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/Zephyr-Core-3.6.0/dts/arm/st/l4/
Dstm32l4p5.dtsi36 rcc: rcc@40021000 { label
41 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00040000>,
42 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
53 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>;
61 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
69 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000020>;
77 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>;
85 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000100>;
92 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
101 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
[all …]
Dstm32l496.dtsi23 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00040000>,
24 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
33 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000002>;
47 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000100>;
56 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x04000000>; //RCC_APB1ENR1_CAN2EN
65 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00010000>;
72 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00001000>,
73 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
77 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000400>,
78 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
Dstm32l431.dtsi27 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>;
35 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
43 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00040000>,
44 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
52 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
64 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
74 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
82 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
91 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
107 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
[all …]
Dstm32l451.dtsi28 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>;
36 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
41 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00040000>,
42 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
51 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
63 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000002>;
74 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
84 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
92 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
101 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
[all …]
Dstm32l471.dtsi20 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>;
28 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
36 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000020>;
44 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>;
51 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
60 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
69 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
81 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
92 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
102 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
[all …]
/Zephyr-Core-3.6.0/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/
Dg0_i2c1_hsi_lptim1_lse_adc1_pllp.overlay31 &rcc {
59 &rcc {
68 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>,
69 <&rcc STM32_SRC_HSI I2C1_SEL(2)>;
74 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
75 <&rcc STM32_SRC_LSE LPTIM1_SEL(3)>;
80 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00100000>,
81 <&rcc STM32_SRC_PLL_P ADC_SEL(1)>;
Dwl_i2c1_hsi_lptim1_lse_adc1_pllp.overlay39 &rcc {
73 &rcc {
85 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>,
86 <&rcc STM32_SRC_HSI I2C1_SEL(2)>;
93 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
94 <&rcc STM32_SRC_LSE LPTIM1_SEL(3)>;
99 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000200>,
100 <&rcc STM32_SRC_PLL_P ADC_SEL(2)>;
Dl4_i2c1_hsi_lptim1_lse.overlay36 &rcc {
64 &rcc {
75 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>,
76 <&rcc STM32_SRC_HSI I2C1_SEL(2)>,
77 <&rcc STM32_SRC_SYSCLK I2C1_SEL(1)>;
82 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
83 <&rcc STM32_SRC_LSE LPTIM1_SEL(3)>;
Dl4_i2c1_sysclk_lptim1_lsi.overlay36 &rcc {
64 &rcc {
75 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>,
76 <&rcc STM32_SRC_SYSCLK I2C1_SEL(1)>,
77 <&rcc STM32_SRC_HSI I2C1_SEL(2)>;
82 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
83 <&rcc STM32_SRC_LSI LPTIM1_SEL(1)>;
/Zephyr-Core-3.6.0/dts/arm/st/mp1/
Dstm32mp157.dtsi44 rcc: rcc@50000000 { label
45 compatible = "st,stm32mp1-rcc";
50 compatible = "st,stm32-rcc-rctl";
88 clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000001>;
96 clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000002>;
104 clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000004>;
112 clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000008>;
120 clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000010>;
128 clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000020>;
136 clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000040>;
[all …]
/Zephyr-Core-3.6.0/dts/arm/st/h5/
Dstm32h562.dtsi29 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
37 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000020>;
45 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>;
53 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000100>;
60 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
69 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
78 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>;
87 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
96 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000001>;
105 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x04000000>;
[all …]
/Zephyr-Core-3.6.0/dts/arm/st/h7/
Dstm32h7.dtsi134 clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000100>;
140 rcc: rcc@58024400 { label
141 compatible = "st,stm32h7-rcc";
146 compatible = "st,stm32-rcc-rctl";
177 clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000001>;
185 clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000002>;
193 clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000004>;
201 clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000008>;
209 clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000010>;
217 clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000020>;
[all …]
/Zephyr-Core-3.6.0/dts/arm/st/f7/
Dstm32f765.dtsi37 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000200>;
45 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000400>;
55 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x01000000>;
66 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00200000>;
77 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x02000000>,
78 <&rcc STM32_CLOCK_BUS_AHB1 0x04000000>,
79 <&rcc STM32_CLOCK_BUS_AHB1 0x08000000>,
80 <&rcc STM32_CLOCK_BUS_AHB1 0x10000000>;
87 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000080>,
88 <&rcc STM32_SRC_PLL_Q SDMMC2_SEL(0)>;
Dstm32f7.dtsi94 clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000001>;
122 rcc: rcc@40023800 { label
123 compatible = "st,stm32-rcc";
128 compatible = "st,stm32-rcc-rctl";
159 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000001>;
167 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000002>;
175 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000004>;
183 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000008>;
191 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000010>;
199 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>;
[all …]
Dstm32f745.dtsi35 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000200>;
43 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000400>;
53 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x01000000>;
64 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00200000>;
74 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x04000000>;
85 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x02000000>,
86 <&rcc STM32_CLOCK_BUS_AHB1 0x04000000>,
87 <&rcc STM32_CLOCK_BUS_AHB1 0x08000000>,
88 <&rcc STM32_CLOCK_BUS_AHB1 0x10000000>;
/Zephyr-Core-3.6.0/dts/arm/st/f2/
Dstm32f2.dtsi94 rcc: rcc@40023800 { label
95 compatible = "st,stm32-rcc";
100 compatible = "st,stm32-rcc-rctl";
131 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000001>;
139 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000002>;
147 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000004>;
155 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000008>;
163 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000010>;
171 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>;
179 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000040>;
[all …]
/Zephyr-Core-3.6.0/dts/arm/st/g4/
Dstm32g4.dtsi108 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00002000>;
123 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00002000>;
138 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00010000>;
146 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00040000>;
155 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000100>;
170 rcc: rcc@40021000 { label
171 compatible = "st,stm32-rcc";
177 compatible = "st,stm32-rcc-rctl";
208 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000001>;
216 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000002>;
[all …]
/Zephyr-Core-3.6.0/dts/arm/st/f4/
Dstm32f446.dtsi26 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
37 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
46 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
55 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
66 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
77 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x06000000>;
85 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000080>,
86 <&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>;
98 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x20000000>,
99 <&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>;
[all …]
Dstm32f405.dtsi26 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>;
34 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000040>;
42 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000100>;
49 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
58 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
67 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
76 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
92 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
108 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000002>;
131 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000040>;
[all …]
Dstm32f412.dtsi32 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>;
40 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000040>;
47 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
58 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
68 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
78 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
89 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
105 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000002>;
128 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000040>;
150 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000080>;
[all …]
/Zephyr-Core-3.6.0/dts/arm/st/f3/
Dstm32f373.dtsi14 rcc: rcc@40021000 { label
17 * prescaler in the RCC register
19 compatible = "st,stm32f1-rcc";
28 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00200000>;
38 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>,
42 <&rcc STM32_SRC_SYSCLK I2C2_SEL(1)>;
53 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
63 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
71 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
88 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
[all …]
/Zephyr-Core-3.6.0/dts/arm/st/u5/
Dstm32u5.dtsi161 rcc: rcc@46020c00 { label
162 compatible = "st,stm32u5-rcc";
168 compatible = "st,stm32-rcc-rctl";
205 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000001>;
213 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000002>;
221 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000004>;
229 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>;
237 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
245 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000020>;
253 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>;
[all …]
/Zephyr-Core-3.6.0/dts/bindings/clock/
Dst,stm32f1-rcc.yaml6 Adds the ADC prescaler to the standard generic STM32 RCC.
7 For more description confere st,stm32-rcc.yaml
9 compatible: "st,stm32f1-rcc"
11 include: st,stm32-rcc.yaml
/Zephyr-Core-3.6.0/dts/arm/st/f1/
Dstm32f103Xc.dtsi29 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
38 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
47 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
64 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
75 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
88 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
96 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
109 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000080>;
117 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000100>;
124 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000400>;
[all …]
/Zephyr-Core-3.6.0/dts/arm/st/l5/
Dstm32l5.dtsi127 clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000100>;
145 rcc: rcc@40021000 { label
146 compatible = "st,stm32-rcc";
153 compatible = "st,stm32-rcc-rctl";
189 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000001>;
197 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000002>;
205 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000004>;
213 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>;
221 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
229 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000020>;
[all …]

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