| /Zephyr-Core-3.7.0/dts/bindings/gpio/ |
| D | renesas,ra-gpio.yaml | 14 port-irq0-pins:
16 description: Pins allow to assign port-irq0
18 port-irq1-pins:
20 description: Pins allow to assign port-irq1
22 port-irq2-pins:
24 description: Pins allow to assign port-irq2
26 port-irq3-pins:
28 description: Pins allow to assign port-irq3
30 port-irq4-pins:
32 description: Pins allow to assign port-irq4
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| /Zephyr-Core-3.7.0/subsys/net/lib/ptp/ |
| D | port.h | 8 * @file port.h
9 * @brief PTP port data structure and interface to operate on PTP Ports.
36 * @brief Structure describing PTP Port.
41 /** PTP Port Dataset*/
43 /** Interface related to the Port. */
51 /** Structure of system timers used by the Port. */
71 /** Pointer to the Port's best Foreign TimeTransmitter. */
86 * @brief Function initializing PTP Port.
94 * @brief Function returning PTP Port's state.
96 * @param[in] port Pointer to the PTP Port structure.
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| D | port.c | 18 #include "port.h"
82 static int port_msg_send(struct ptp_port *port, struct ptp_msg *msg, enum ptp_socket idx) in port_msg_send() argument
86 return ptp_transport_send(port, msg, idx); in port_msg_send()
117 static void port_synchronize(struct ptp_port *port, in port_synchronize() argument
131 port_timer_set_timeout(&port->timers.sync, in port_synchronize()
132 port->port_ds.announce_receipt_timeout, in port_synchronize()
133 port->port_ds.log_sync_interval); in port_synchronize()
136 static void port_ds_init(struct ptp_port *port) in port_ds_init() argument
138 struct ptp_port_ds *ds = &port->port_ds; in port_ds_init()
157 struct ptp_port *port = ptp_clock_port_from_iface(pkt->iface); in port_delay_req_timestamp_cb() local
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| D | transport.h | 17 #include "port.h"
27 * @brief Values used to identify PTP Port socket based on used port.
47 * @param[in] port Pointer to the PTP Port structure.
51 int ptp_transport_open(struct ptp_port *port);
56 * @param[in] port Pointer to the PTP Port structure.
60 int ptp_transport_close(struct ptp_port *port);
68 * @param[in] port Pointer to the PTP Port structure.
74 int ptp_transport_send(struct ptp_port *port, struct ptp_msg *msg, enum ptp_socket idx);
80 * @param[in] port Pointer to the PTP Port structure.
86 int ptp_transport_sendto(struct ptp_port *port, struct ptp_msg *msg, enum ptp_socket idx);
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| /Zephyr-Core-3.7.0/include/zephyr/drivers/interrupt_controller/ |
| D | sam0_eic.h | 33 * @brief Acquire an EIC interrupt for specific port and pin combination
35 * This acquires the EIC interrupt for a specific port and pin combination,
37 * callback per port is supported and supplying a different one will
38 * change it for all lines on that port.
40 * @param port port index (A=0, etc)
41 * @param pin pin in the port
47 int sam0_eic_acquire(int port, int pin, enum sam0_eic_trigger trigger,
51 * @brief Release the EIC interrupt for a specific port and pin combination
53 * Release the EIC configuration for a specific port and pin combination.
57 * @param port port index (A=0, etc)
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| /Zephyr-Core-3.7.0/tests/drivers/gpio/gpio_api_1pin/src/ |
| D | test_port.c | 14 static void port_get_raw_and_verify(const struct device *port, in port_get_raw_and_verify() argument
20 zassert_equal(gpio_port_get_raw(port, &val_actual), 0, in port_get_raw_and_verify()
21 "Test point %d: failed to get physical port value", idx); in port_get_raw_and_verify()
23 "Test point %d: invalid physical port get value", idx); in port_get_raw_and_verify()
26 static void port_get_and_verify(const struct device *port, in port_get_and_verify() argument
32 zassert_equal(gpio_port_get(port, &val_actual), 0, in port_get_and_verify()
33 "Test point %d: failed to get logical port value", idx); in port_get_and_verify()
35 "Test point %d: invalid logical port get value", idx); in port_get_and_verify()
38 static void port_set_masked_raw_and_verify(const struct device *port, in port_set_masked_raw_and_verify() argument
42 zassert_equal(gpio_port_set_masked_raw(port, mask, value), 0, in port_set_masked_raw_and_verify()
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| D | test_pin.c | 12 static void pin_get_raw_and_verify(const struct device *port, in pin_get_raw_and_verify() argument
18 val_actual = gpio_pin_get_raw(port, pin); in pin_get_raw_and_verify()
25 static void pin_get_and_verify(const struct device *port, unsigned int pin, in pin_get_and_verify() argument
30 val_actual = gpio_pin_get(port, pin); in pin_get_and_verify()
37 static void pin_set_raw_and_verify(const struct device *port, in pin_set_raw_and_verify() argument
41 zassert_equal(gpio_pin_set_raw(port, pin, val), 0, in pin_set_raw_and_verify()
46 static void pin_set_and_verify(const struct device *port, unsigned int pin, in pin_set_and_verify() argument
50 zassert_equal(gpio_pin_set(port, pin, val), 0, in pin_set_and_verify()
62 const struct device *port; in ZTEST() local
66 port = DEVICE_DT_GET(TEST_NODE); in ZTEST()
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| D | test_config.c | 15 static void pin_get_raw_and_verify(const struct device *port, in pin_get_raw_and_verify() argument
21 val_actual = gpio_pin_get_raw(port, pin); in pin_get_raw_and_verify()
28 static void pin_set_raw_and_verify(const struct device *port, in pin_set_raw_and_verify() argument
32 zassert_equal(gpio_pin_set_raw(port, pin, val), 0, in pin_set_raw_and_verify()
50 const struct device *port; in ZTEST() local
53 port = DEVICE_DT_GET(TEST_NODE); in ZTEST()
54 zassert_true(device_is_ready(port), "GPIO dev is not ready"); in ZTEST()
56 TC_PRINT("Running test on port=%s, pin=%d\n", port->name, TEST_PIN); in ZTEST()
58 ret = gpio_pin_configure(port, TEST_PIN, GPIO_OUTPUT); in ZTEST()
61 pin_set_raw_and_verify(port, TEST_PIN, 1, TEST_POINT(1)); in ZTEST()
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| /Zephyr-Core-3.7.0/drivers/xen/ |
| D | events.c | 28 /* data is the event_channels entry, subtracting the base, it's the port */ in empty_callback()
29 unsigned int port = (((evtchn_handle_t *)data) - event_channels); in empty_callback() local
31 events_missed[port] = true; in empty_callback()
44 rc = alloc.port; in alloc_unbound_event_channel()
61 rc = alloc.port; in alloc_unbound_event_channel_dom0()
95 int evtchn_close(evtchn_port_t port) in evtchn_close() argument
98 .port = port, in evtchn_close()
104 int evtchn_set_priority(evtchn_port_t port, uint32_t priority) in evtchn_set_priority() argument
107 .port = port, in evtchn_set_priority()
114 void notify_evtchn(evtchn_port_t port) in notify_evtchn() argument
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| /Zephyr-Core-3.7.0/subsys/net/l2/ethernet/gptp/ |
| D | gptp_private.h | 28 #define GPTP_STATS_INC(port, var) (GPTP_PORT_PARAM_DS(port)->var++) argument
30 #define GPTP_STATS_INC(port, var)
36 * Utility to check if a port is configured as a slave.
38 * @param port Port to check.
40 * @return True if this is a slave port.
42 bool gptp_is_slave_port(int port);
45 * @brief Convert the network interface to the correct port number.
47 * @param iface Network Interface acting as a ptp port.
49 * @return Number of the port if found, ENODEV otherwise.
79 * @param port Port number.
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| D | gptp_mi.c | 72 void gptp_change_port_state_debug(int port, enum gptp_port_state state, in gptp_change_port_state_debug() argument
76 void gptp_change_port_state(int port, enum gptp_port_state state) in gptp_change_port_state_debug()
81 if (global_ds->selected_role[port] == state) { in gptp_change_port_state_debug()
86 NET_DBG("[%d] state %s -> %s (%s():%d)", port, in gptp_change_port_state_debug()
87 state2str(global_ds->selected_role[port]), in gptp_change_port_state_debug()
91 global_ds->selected_role[port] = state; in gptp_change_port_state_debug()
96 int port, in gptp_change_pa_info_state_debug() argument
103 int port, in gptp_change_pa_info_state_debug()
113 NET_DBG("[%d] PA info state %s -> %s (%s():%d)", port, in gptp_change_pa_info_state_debug()
124 int port; in gptp_mi_half_sync_itv_timeout() local
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| D | gptp_messages.h | 252 /** Source Port Id of the Path Delay Request. */
266 /** Source Port Id of the Path Delay Request. */
305 /** Target Port Identity , always 0xFF. */
329 * @param port gPTP port number.
333 struct net_pkt *gptp_prepare_sync(int port);
338 * @param port gPTP port number.
342 struct net_pkt *gptp_prepare_follow_up(int port, struct net_pkt *sync);
347 * @param port gPTP port number.
351 struct net_pkt *gptp_prepare_pdelay_req(int port);
356 * @param port gPTP port number.
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| D | gptp_mi.h | 35 /** Port to which the Sync Information belongs to. */
45 * @brief Run all Media Independent Port Sync State Machines.
47 * @param port Number of the port the State Machines needs to be run on.
49 void gptp_mi_port_sync_state_machines(int port);
52 * @brief Run all Media Independent Port BMCA State Machines.
54 * @param port Number of the port the State Machines needs to be run on.
56 void gptp_mi_port_bmca_state_machines(int port);
66 * @param port Port number of the clock to use.
70 uint64_t gptp_get_current_time_nanosecond(int port);
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| /Zephyr-Core-3.7.0/include/zephyr/arch/arc/v2/ |
| D | sys_io.h | 26 void sys_out8(uint8_t data, io_port_t port) in sys_out8() argument
28 z_arc_v2_aux_reg_write(port, data); in sys_out8()
32 uint8_t sys_in8(io_port_t port) in sys_in8() argument
34 return (uint8_t)(z_arc_v2_aux_reg_read(port) & 0x000000ff); in sys_in8()
38 void sys_out16(uint16_t data, io_port_t port) in sys_out16() argument
40 z_arc_v2_aux_reg_write(port, data); in sys_out16()
44 uint16_t sys_in16(io_port_t port) in sys_in16() argument
46 return (uint16_t)(z_arc_v2_aux_reg_read(port) & 0x0000ffff); in sys_in16()
50 void sys_out32(uint32_t data, io_port_t port) in sys_out32() argument
52 z_arc_v2_aux_reg_write(port, data); in sys_out32()
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| /Zephyr-Core-3.7.0/drivers/gpio/ |
| D | gpio_handlers.c | 10 static inline int z_vrfy_gpio_pin_configure(const struct device *port, in z_vrfy_gpio_pin_configure() argument
14 K_OOPS(K_SYSCALL_DRIVER_GPIO(port, pin_configure)); in z_vrfy_gpio_pin_configure()
15 return z_impl_gpio_pin_configure((const struct device *)port, in z_vrfy_gpio_pin_configure()
22 static inline int z_vrfy_gpio_pin_get_config(const struct device *port, in z_vrfy_gpio_pin_get_config() argument
26 K_OOPS(K_SYSCALL_DRIVER_GPIO(port, pin_get_config)); in z_vrfy_gpio_pin_get_config()
29 return z_impl_gpio_pin_get_config(port, pin, flags); in z_vrfy_gpio_pin_get_config()
34 static inline int z_vrfy_gpio_port_get_raw(const struct device *port, in z_vrfy_gpio_port_get_raw() argument
37 K_OOPS(K_SYSCALL_DRIVER_GPIO(port, port_get_raw)); in z_vrfy_gpio_port_get_raw()
39 return z_impl_gpio_port_get_raw((const struct device *)port, in z_vrfy_gpio_port_get_raw()
44 static inline int z_vrfy_gpio_port_set_masked_raw(const struct device *port, in z_vrfy_gpio_port_set_masked_raw() argument
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| D | gpio_emul.c | 108 * @param port The emulated GPIO device pointer
115 get_pins_with_flags(const struct device *port, gpio_port_pins_t mask, in get_pins_with_flags() argument
121 (struct gpio_emul_data *)port->data; in get_pins_with_flags()
123 (const struct gpio_emul_config *)port->config; in get_pins_with_flags()
139 * @param port The emulated GPIO device pointer
143 static inline gpio_port_pins_t get_input_pins(const struct device *port) in get_input_pins() argument
145 return get_pins_with_flags(port, GPIO_INPUT, GPIO_INPUT); in get_input_pins()
153 * @param port The emulated GPIO device pointer
157 static inline gpio_port_pins_t get_output_pins(const struct device *port) in get_output_pins() argument
159 return get_pins_with_flags(port, GPIO_OUTPUT, GPIO_OUTPUT); in get_output_pins()
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| D | gpio_andes_atcgpio100.c | 97 static int gpio_atcgpio100_config(const struct device *port, in gpio_atcgpio100_config() argument
101 struct gpio_atcgpio100_data * const data = port->data; in gpio_atcgpio100_config()
119 sys_write32(pin_mask, GPIO_DSET(port)); in gpio_atcgpio100_config()
121 sys_write32(pin_mask, GPIO_DCLR(port)); in gpio_atcgpio100_config()
127 port_value = sys_read32(GPIO_DIR(port)); in gpio_atcgpio100_config()
128 sys_write32((port_value | pin_mask), GPIO_DIR(port)); in gpio_atcgpio100_config()
145 sys_write32(DF_DEBOUNCED_SETTING, GPIO_DEBC(port)); in gpio_atcgpio100_config()
146 port_value = sys_read32(GPIO_DEBE(port)); in gpio_atcgpio100_config()
147 sys_write32((port_value | pin_mask), GPIO_DEBE(port)); in gpio_atcgpio100_config()
151 port_value = sys_read32(GPIO_DIR(port)); in gpio_atcgpio100_config()
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| D | gpio_psoc6.c | 45 GPIO_PRT_Type * const port = cfg->regs; in gpio_psoc6_config() local
80 Cy_GPIO_Pin_FastInit(port, pin, drv_mode, pin_val, HSIOM_SEL_GPIO); in gpio_psoc6_config()
81 Cy_GPIO_SetVtrip(port, pin, CY_GPIO_VTRIP_CMOS); in gpio_psoc6_config()
82 Cy_GPIO_SetSlewRate(port, pin, CY_GPIO_SLEW_FAST); in gpio_psoc6_config()
83 Cy_GPIO_SetDriveSel(port, pin, CY_GPIO_DRIVE_FULL); in gpio_psoc6_config()
86 (unsigned int) port, pin, drv_mode, pin_val); in gpio_psoc6_config()
95 GPIO_PRT_Type * const port = cfg->regs; in gpio_psoc6_port_get_raw() local
97 *value = GPIO_PRT_IN(port); in gpio_psoc6_port_get_raw()
99 LOG_DBG("P: 0x%08x, V: 0x%08x", (unsigned int) port, *value); in gpio_psoc6_port_get_raw()
109 GPIO_PRT_Type * const port = cfg->regs; in gpio_psoc6_port_set_masked_raw() local
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| /Zephyr-Core-3.7.0/dts/arm/renesas/ra/ |
| D | ra-cm4-common.dtsi | 131 interrupt-names = "port-irq2", "port-irq3", "port-irq6",
132 "port-irq7", "port-irq10", "port-irq15";
133 port-irq2-pins = <2>;
134 port-irq3-pins = <4>;
135 port-irq6-pins = <0>;
136 port-irq7-pins = <1 15>;
137 port-irq10-pins = <5>;
138 port-irq15-pins = <11>;
152 interrupt-names = "port-irq0", "port-irq1", "port-irq2",
153 "port-irq3", "port-irq4";
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| /Zephyr-Core-3.7.0/drivers/misc/timeaware_gpio/ |
| D | timeaware_gpio_handlers.c | 9 static inline int z_vrfy_tgpio_port_get_time(const struct device *port, uint64_t *current_time) in z_vrfy_tgpio_port_get_time() argument
11 K_OOPS(Z_SYSCALL_DRIVER_TGPIO(port, get_time)); in z_vrfy_tgpio_port_get_time()
13 return z_impl_tgpio_port_get_time((const struct device *)port, (uint64_t *)current_time); in z_vrfy_tgpio_port_get_time()
17 static inline int z_vrfy_tgpio_port_get_cycles_per_second(const struct device *port, in z_vrfy_tgpio_port_get_cycles_per_second() argument
20 K_OOPS(Z_SYSCALL_DRIVER_TGPIO(port, cyc_per_sec)); in z_vrfy_tgpio_port_get_cycles_per_second()
22 return z_impl_tgpio_port_get_cycles_per_second((const struct device *)port, in z_vrfy_tgpio_port_get_cycles_per_second()
27 static inline int z_vrfy_tgpio_pin_periodic_output(const struct device *port, uint32_t pin, in z_vrfy_tgpio_pin_periodic_output() argument
31 K_OOPS(Z_SYSCALL_DRIVER_TGPIO(port, set_perout)); in z_vrfy_tgpio_pin_periodic_output()
32 return z_impl_tgpio_pin_periodic_output((const struct device *)port, pin, start_time, in z_vrfy_tgpio_pin_periodic_output()
37 static inline int z_vrfy_tgpio_pin_disable(const struct device *port, uint32_t pin) in z_vrfy_tgpio_pin_disable() argument
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| /Zephyr-Core-3.7.0/drivers/serial/ |
| D | Kconfig.sifive | 15 # ---------- Port 0 ----------
18 bool "SIFIVE Port 0"
21 This tells the driver to configure the UART port at boot, depending on
25 int "Port 0 RX Interrupt Threshold Count"
29 Port 0 RX Threshold at which the RX FIFO interrupt triggers.
32 int "Port 0 TX Interrupt Threshold Count"
36 Port 0 TX Threshold at which the TX FIFO interrupt triggers.
38 # ---------- Port 1 ----------
41 bool "SIFIVE Port 1"
44 This tells the driver to configure the UART port at boot, depending on
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| /Zephyr-Core-3.7.0/drivers/pinctrl/renesas/rz/ |
| D | pinctrl_rzt2m.c | 16 /* Port m mode control register */
17 #define PMC(port) (PORT_NSR + 0x400 + port) argument
18 /* Port m function control register */
19 #define PFC(port) (PORT_NSR + 0x600 + (0x4 * port)) argument
21 #define DRCTL(port, pin) (PORT_NSR + 0xa00 + (0x8 * port) + pin) argument
22 /* Port m region select register */
23 #define RSELP(port) (PTADR + port) argument
36 uint8_t rselp = sys_read8(RSELP(pin->port)); in pinctrl_configure_pin()
37 uint32_t pfc = sys_read32(PFC(pin->port)) & ~(PFC_FUNC_MASK(pin->pin)); in pinctrl_configure_pin()
38 uint8_t pmc = sys_read8(PMC(pin->port)); in pinctrl_configure_pin()
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| /Zephyr-Core-3.7.0/drivers/pinctrl/ |
| D | pinctrl_numicro.c | 26 #define REG_MFP(port, pin) (*(volatile uint32_t *)((uint32_t)DT_INST_REG_ADDR_BY_NAME(0, mfp) + \ argument
27 ((port) * 8) + \
30 #define REG_MFOS(port) (*(volatile uint32_t *)((uint32_t)DT_INST_REG_ADDR_BY_NAME(0, mfos) + \ argument
31 ((port) * 4)))
35 /** Utility macro that expands to the GPIO port address if it exists */
40 /** Port addresses */
55 GPIO_T *port; in gpio_configure() local
65 port = (GPIO_T *)gpio_port_addrs[port_idx]; in gpio_configure()
73 port->MODE = (port->MODE & ~MODE_MASK(pin_idx)) | in gpio_configure()
75 port->DBEN = (port->DBEN & ~BIT(pin_idx)) | in gpio_configure()
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| /Zephyr-Core-3.7.0/include/zephyr/sys/ |
| D | sys_io.h | 1 /* Port and memory mapped registers I/O operations */
23 /* Port I/O functions */
26 * @fn static inline void sys_out8(uint8_t data, io_port_t port);
27 * @brief Output a byte to an I/O port
29 * This function writes a byte to the given port.
32 * @param port the port address where to write the byte
36 * @fn static inline uint8_t sys_in8(io_port_t port);
37 * @brief Input a byte from an I/O port
39 * This function reads a byte from the port.
41 * @param port the port address from where to read the byte
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| /Zephyr-Core-3.7.0/include/zephyr/dt-bindings/pinctrl/renesas/ |
| D | pinctrl-ra-common.h | 25 #define RA_PINCFG(port, pin, psel, opt) \ argument
27 (((port)&PORT_MASK) << PORT_POS) | ((((port) >> 3) & PORT4_MASK) << PORT4_POS) | \
31 #define RA_PINCFG__40(port, pin, psel, opt) RA_PINCFG(port, pin, psel, opt) argument
35 #define RA_PINCFG__48(port, pin, psel, opt) RA_PINCFG(port, pin, psel, opt) argument
39 #define RA_PINCFG__64(port, pin, psel, opt) RA_PINCFG(port, pin, psel, opt) argument
43 #define RA_PINCFG_100(port, pin, psel, opt) RA_PINCFG(port, pin, psel, opt) argument
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