Searched full:ppis (Results 1 – 8 of 8) sorted by relevance
119 * 2 adjacent PPIs (9 & 10) and 2 adjacent PPI groups are used for this wiring;140 * 2 adjacent PPIs (12 & 13) are used for this wiring; <index> must be 0 or 1.168 * Note: Use the same number of PPIs as for PHY CODED HAL_SW_SWITCH_RADIO_ENABLE_S2_PPI_BASE.176 * Note: Use the same number of PPIs as for PHY CODED: HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI.
344 * 2 adjacent PPIs (9 & 10) and 2 adjacent PPI groups are used for this wiring;374 * 2 adjacent PPIs (12 & 13) are used for this wiring; <index> must be 0 or 1.419 * double buffers implementation works for sw_switch using PPIs, in hal_radio_b2b_txen_on_sw_switch()421 * the next PPIs task to be Radio Tx enable. in hal_radio_b2b_txen_on_sw_switch()445 * double buffers implementation works for sw_switch using PPIs, in hal_radio_b2b_rxen_on_sw_switch()447 * the next PPIs task to be Radio Tx enable. in hal_radio_b2b_rxen_on_sw_switch()614 * Disable of the group of PPIs responsible for handling of software based switch is done by
285 * 2 adjacent PPIs (14 & 15) and 2 adjacent PPI groups are used for this wiring;651 * tasks are going to be subscribed on the same PPIs. in hal_radio_sw_switch_ppi_group_setup()700 * Disable of the group of PPIs responsible for handling of software based switch is done by
110 * 2 adjacent PPIs (14 & 15) and 2 adjacent PPI groups are used for this wiring;
735 * PPIs related with the Radio operation switch.
15 per-processor interrupts via PPIs.
9 route to specific Private Peripheral Interrupts (PPIs) of the corresponding
399 /* Configure all SGIs/PPIs as G1S or G1NS depending on Zephyr in gicv3_cpuif_init()414 /* Configure PPIs as level triggered */ in gicv3_cpuif_init()
