1# Copyright (c) 2021, Linaro ltd
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  PLL2 node binding for Connectivity line devices (STM32F105/STM32F107)
6
7  Takes clk_hse as input clock, using prediv as prescaler.
8
9  Each PLL as its own output clock.
10
11    f(PLL2CLK) = f(PLL2IN) / PREDIV * PLLMUL --> PLL (System Clock)
12
13
14compatible: "st,stm32f105-pll2-clock"
15
16include:
17  - name: st,stm32f105-pll-clock.yaml
18    property-blocklist:
19      - mul
20
21properties:
22  mul:
23    type: int
24    required: true
25    description: |
26        PLL multiplication factor for output clock
27    enum:
28      - 8
29      - 9
30      - 10
31      - 11
32      - 12
33      - 13
34      - 14
35      - 16
36      - 20
37