1# Copyright (c) 2022, NXP
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  Kinetis pinctrl node. This node will define pin configurations in pin groups,
6  and has the 'pinctrl' node identifier in the SOC's devicetree. Each group
7  within the pin configuration defines the pin configuration for a peripheral,
8  and each numbered subgroup in the pin group defines all the pins for that
9  peripheral with the same configuration properties. The 'pins' property in
10  a group selects the pins to be configured, and the remaining properties set
11  configuration values for those pins. Here is an example group for UART0 pins:
12
13  uart0_default: uart0_default {
14    group0 {
15      pins = <UART0_RX_PTB16
16        UART0_TX_PTB17>;
17      drive-strength = "low";
18      slew-rate = "fast";
19      };
20  };
21
22  If only the required properties are supplied, the pin configuration register
23  will be assigned the following values:
24  PCR_PS=0,
25  PCR_PE=0,
26  PCR_ODE=0,
27  PCR_SRE=<slew-rate selection>,
28  PCR_DSE=<drive-strength selection>,
29  PCR_PFE=0
30
31compatible: "nxp,kinetis-pinctrl"
32
33include: base.yaml
34
35child-binding:
36  description: Kinetis pin controller pin group
37  child-binding:
38    description: |
39      Kinetis pin controller pin configuration node
40
41    include:
42      - name: pincfg-node.yaml
43        property-allowlist:
44          - drive-open-drain
45          - bias-pull-up
46          - bias-pull-down
47
48    properties:
49      pinmux:
50        required: true
51        type: array
52        description: |
53          Pin mux selections for this group. See the soc level pinctrl DTSI file
54          in NXP's HAL for a defined list of these options
55      drive-strength:
56        required: true
57        type: string
58        enum:
59          - "low"
60          - "high"
61        description: |
62          Pin output drive strength. Sets the DSE field in the PORTx_PCRn register.
63          0 DSE_0- low drive strength when pin is configured as output
64          1 DSE_1- high drive strength when pin is configured as output
65      slew-rate:
66        required: true
67        type: string
68        enum:
69          - "fast"
70          - "slow"
71        description: |
72          Pin output slew rate. Sets the SRE field in the PORTx_PCRn register.
73          0 SRE_0_fast- fast slew rate when pin is configured as output
74          1 SRE_1_slow- slow slew rate when pin is configured as output
75      nxp,passive-filter:
76        type: boolean
77        description: |
78          Enable passive filter on pin. Sets the PFE field in the PORTx_PCRn register.
79