Searched full:pclk1 (Results 1 – 5 of 5) sorted by relevance
| /Zephyr-Core-3.6.0/drivers/i2c/ |
| D | i2c_gd32.c | 498 uint32_t pclk1, freq, clkc; in i2c_gd32_configure() local
508 &pclk1); in i2c_gd32_configure()
511 freq = pclk1 / 1000000U; in i2c_gd32_configure()
529 * T_pclk1 is reciprocal of pclk1: in i2c_gd32_configure()
530 * T_pclk1 = 1 / pclk1 in i2c_gd32_configure()
537 * CLKC = pclk1 / (bitrate * 2) in i2c_gd32_configure()
539 * CLKC = pclk1 / (bitrate * 25) in i2c_gd32_configure()
544 * T_pclk1: duration of single pclk1 pulse in i2c_gd32_configure()
545 * pclk1: i2c device clock frequency in i2c_gd32_configure()
566 /* CLKC = pclk1 / (bitrate * 2) */ in i2c_gd32_configure()
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| /Zephyr-Core-3.6.0/soc/arm/nuvoton_numicro/m48x/ |
| D | soc.c | 27 /* Set both PCLK0 and PCLK1 as HCLK/2 */ in z_arm_platform_init()
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| /Zephyr-Core-3.6.0/dts/bindings/clock/ |
| D | st,stm32-rcc.yaml | 16 Last, peripheral bus clocks (typically PCLK1, PCLK2) should be configured using matching
64 'PCLK/PCLK1/PCLK2' depending on the device). There is no need to add a second
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| D | st,stm32h7-rcc.yaml | 15 Last, bus clocks (typically HCLK, PCLK1, PCLK2) should be configured using matching
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| D | st,stm32wba-rcc.yaml | 16 Last, peripheral bus clocks (typically PCLK1, PCLK2, PCLK7) should be configured using
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