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/Zephyr-latest/drivers/pcie/host/
DKconfig1 # PCIe/new PCI configuration options
6 menuconfig PCIE config
7 bool "New PCI/PCIe Root Complex support"
11 if PCIE
13 module = PCIE
14 module-str = pcie
18 int "PCIe initialization priority"
21 PCIe host drivers initialization priority.
24 bool "PCIe Controller management"
26 Add support for PCIe Controller management when not handled by a
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Dptm.c9 LOG_MODULE_REGISTER(pcie);
21 #include <zephyr/drivers/pcie/pcie.h>
30 cap.raw = pcie_conf_read(config->pcie->bdf, base + PTM_CAP_REG_OFFSET); in pcie_ptm_root_setup()
32 LOG_ERR("PTM root not supported on 0x%x", config->pcie->bdf); in pcie_ptm_root_setup()
39 pcie_conf_write(config->pcie->bdf, base + PTM_CTRL_REG_OFFSET, ctrl.raw); in pcie_ptm_root_setup()
41 LOG_DBG("PTM root 0x%x enabled", config->pcie->bdf); in pcie_ptm_root_setup()
51 reg = pcie_get_ext_cap(config->pcie->bdf, PCIE_EXT_CAP_ID_PTM); in pcie_ptm_root_init()
53 LOG_ERR("PTM capability not exposed on 0x%x", config->pcie->bdf); in pcie_ptm_root_init()
63 DEVICE_PCIE_INST_INIT(index, pcie), \
Dptm.h10 #include <zephyr/drivers/pcie/pcie.h>
11 #include <zephyr/drivers/pcie/cap.h>
41 struct pcie_dev *pcie; member
/Zephyr-latest/drivers/pcie/endpoint/
DKconfig.iproc1 # iProc PCIe EP configuration options
7 bool "Broadcom iProc PCIe EP driver"
9 This option enables Broadcom iProc PCIe EP driver.
14 bool "Re-initialize PCIe MSI/MSIX configurations"
17 bool "Version-2 of iProc PCIe EP controller"
DKconfig1 # PCIe Endpoint configuration options
7 bool "PCIe Endpoint support"
9 This option enables PCIe Endpoint support.
17 comment "PCIe Endpoint Drivers"
19 source "drivers/pcie/endpoint/Kconfig.iproc"
Dpcie_ep_common.c8 #include <zephyr/drivers/pcie/endpoint/pcie_ep.h>
14 * PCIe writes (posted) have reached Host, i.e. to flush PCIe writes,
15 * we need to add a dummy PCIe read (non posted transaction) after each
19 * a dummy PCIe read.
23 * on mapped Host address to generate a dummy PCIe read, before unmapping the
26 * Basically, we issue single byte PCIe read with sys_read8.
32 * In this case, we need to *explicitly* perform PCIe read.
35 * | Core | Data transfer with | OB memory type | Dummy PCIe read |
49 * | Cortex-M7) | | highmem | Explicit PCIe read |
56 * are implemented with dummy PCIe read, phew!
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/Zephyr-latest/dts/bindings/pcie/endpoint/
Dbrcm,iproc-pcie-ep.yaml4 description: Broadcom iProc PCIe EP node
6 compatible: "brcm,iproc-pcie-ep"
14 Register space for the memory mapped PAX(PCIe to AXI bridge) registers,
16 and to map Host PCIe address to PCIe Outbound memory.
/Zephyr-latest/dts/bindings/pcie/host/
Dpcie-controller.yaml4 # Common fields for PCIe bus controllers
8 description: Generic PCIe host controller
10 compatible: "pcie-controller"
12 bus: pcie
Dptm-root.yaml4 # Common fields for PCIe PTM root
6 include: [base.yaml, pcie-device.yaml]
/Zephyr-latest/drivers/pcie/
DKconfig1 # PCIe RC/EP drivers configuration options
3 source "drivers/pcie/host/Kconfig"
4 source "drivers/pcie/endpoint/Kconfig"
/Zephyr-latest/boards/qemu/cortex_a53/
Dqemu_cortex_a53.dts25 zephyr,pcie-controller = &pcie;
42 &pcie {
43 eth0: pcie@1,0 {
48 interrupt-parent = <&pcie>;
DKconfig.defconfig25 default 0x80000000 if PCIE
29 default ARM64_VA_BITS_40 if PCIE
33 default ARM64_PA_BITS_40 if PCIE
/Zephyr-latest/dts/bindings/test/
Dvnd,pcie.yaml4 description: Test PCIe bus controller
6 compatible: vnd,pcie
10 bus: pcie
/Zephyr-latest/include/zephyr/drivers/pcie/
Dvc.h11 * @brief PCIe Virtual Channel Host Interface
12 * @defgroup pcie_vc_host_interface PCIe Virtual Channel Host Interface
25 #include <zephyr/drivers/pcie/pcie.h>
54 * @brief Enable PCIe Virtual Channel handling
65 * @brief Disable PCIe Virtual Channel handling
72 * @brief Map PCIe TC/VC
/Zephyr-latest/include/zephyr/drivers/pcie/endpoint/
Dpcie_ep.h4 * @brief Public APIs for the PCIe EP drivers.
22 PCIE_OB_ANYMEM, /**< PCIe OB window within any address range */
23 PCIE_OB_LOWMEM, /**< PCIe OB window within 32-bit address range */
24 PCIE_OB_HIGHMEM, /**< PCIe OB window above 32-bit address range */
47 * @brief Callback API for PCIe reset interrupts
80 * @brief Read PCIe EP configuration space
101 * @brief Write PCIe EP configuration space
120 * @brief Map a host memory buffer to PCIe outbound region
122 * @details This API maps a host memory buffer to PCIe outbound region,
124 * multiple PCIe outbound regions if supported by SoC
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/Zephyr-latest/drivers/virtualization/
Dvirt_ivshmem.c18 #include <zephyr/drivers/pcie/cap.h>
48 n_vectors = pcie_msi_vectors_allocate(data->pcie->bdf, in ivshmem_configure_msi_x_interrupts()
64 if (!pcie_msi_vector_connect(data->pcie->bdf, in ivshmem_configure_msi_x_interrupts()
75 if (!pcie_msi_enable(data->pcie->bdf, data->vectors, n_vectors, 0)) { in ivshmem_configure_msi_x_interrupts()
98 uint32_t cfg_int = pcie_conf_read(data->pcie->bdf, PCIE_CONF_INTR); in ivshmem_configure_int_x_interrupts()
107 pcie_set_cmd(data->pcie->bdf, PCIE_CONF_CMDSTAT_INTX_DISABLE, false); in ivshmem_configure_int_x_interrupts()
117 data->pcie->bdf, intx->irq, intx->priority, in ivshmem_configure_int_x_interrupts()
125 pcie_irq_enable(data->pcie->bdf, intx->irq); in ivshmem_configure_int_x_interrupts()
163 if (!pcie_get_mbar(data->pcie->bdf, IVSHMEM_PCIE_REG_BAR_IDX, &mbar_regs)) { in ivshmem_configure()
173 pcie_set_cmd(data->pcie->bdf, PCIE_CONF_CMDSTAT_MEM | in ivshmem_configure()
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Dvirt_ivshmem.h10 #include <zephyr/drivers/pcie/pcie.h>
13 #include <zephyr/drivers/pcie/msi.h>
48 struct pcie_dev *pcie; member
/Zephyr-latest/drivers/can/
Dcan_kvaser_pci.c12 #include <zephyr/drivers/pcie/pcie.h>
29 struct pcie_dev *pcie; member
76 if (kvaser_config->pcie->bdf == PCIE_BDF_NONE) { in can_kvaser_pci_init()
77 LOG_ERR("failed to find PCIe device"); in can_kvaser_pci_init()
81 pcie_set_cmd(kvaser_config->pcie->bdf, PCIE_CONF_CMDSTAT_IO, true); in can_kvaser_pci_init()
84 if (!pcie_probe_iobar(kvaser_config->pcie->bdf, 0, &iobar)) { in can_kvaser_pci_init()
92 if (!pcie_probe_iobar(kvaser_config->pcie->bdf, 1, &iobar)) { in can_kvaser_pci_init()
100 if (!pcie_probe_iobar(kvaser_config->pcie->bdf, 2, &iobar)) { in can_kvaser_pci_init()
164 DEVICE_PCIE_INST_INIT(inst, pcie), \
/Zephyr-latest/samples/drivers/ethernet/eth_ivshmem/boards/
Dqemu_cortex_a53.overlay16 /delete-node/ pcie@4010000000;
18 pcie: pcie@8e00000 {
44 &pcie {
52 interrupt-parent = <&pcie>;
/Zephyr-latest/dts/bindings/dma/
Dbrcm,iproc-pax-dma-v1.yaml4 description: Broadcom iProc PAX(PCIE<->AXI) DMA controller version 1
32 pcie-ep:
34 description: Pcie endpoint handle
Dbrcm,iproc-pax-dma-v2.yaml4 description: Broadcom iProc PAX(PCIE<->AXI) DMA controller version 2
32 pcie-ep:
34 description: Pcie endpoint handle
Darm,dma-pl330.yaml18 If PCIe EP client uses channel 0 for Tx DMA and channel 1 for Rx DMA
19 pcie0_ep: pcie@4e100000 {
20 compatible = "brcm,iproc-pcie-ep";
/Zephyr-latest/soc/intel/elkhart_lake/
Dsoc.h30 #if DT_ON_BUS(DT_CHOSEN(zephyr_console), pcie)
31 #include <zephyr/drivers/pcie/pcie.h>
/Zephyr-latest/soc/intel/raptor_lake/
Dsoc.h32 #if DT_ON_BUS(DT_CHOSEN(zephyr_console), pcie)
33 #include <zephyr/drivers/pcie/pcie.h>
/Zephyr-latest/soc/intel/alder_lake/
Dsoc.h34 #if DT_ON_BUS(DT_CHOSEN(zephyr_console), pcie)
35 #include <zephyr/drivers/pcie/pcie.h>

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