1# Copyright (c) 2020, Linaro Limited
2# Copyright (c) 2021, Teslabs Engineering S.L.
3# Copyright (c) 2021-2022, Gerson Fernando Budke <nandojve@gmail.com>
4# SPDX-License-Identifier: Apache-2.0
5
6description: |
7  Atmel SAM Pinctrl container node
8
9  The Atmel SAM pin controller is a singleton node responsible for controlling
10  pin function selection and pin properties. For example, you can use this node
11  to route USART0 RX to pin PA10 and enable the pull-up resistor on the pin.
12
13  The node has the 'pinctrl' node label set in your SoC's devicetree, so you can
14  modify it like this:
15
16    &pinctrl {
17            /* your modifications go here */
18    };
19
20  All device pin configurations should be placed in child nodes of the 'pinctrl'
21  node, as shown in this example:
22
23    /** You can put this in places like a <board>-pinctrl.dtsi file in
24      * your board directory, or a devicetree overlay in your application.
25      */
26
27    /** include pre-defined combinations for the SoC variant used by the board */
28    #include <dt-bindings/pinctrl/sam4sXc-pinctrl.h>
29
30    &pinctrl {
31      /* configuration for the usart0 "default" state */
32      usart0_default: usart0_default {
33        /* group 1 */
34        group1 {
35          /* configure PA6 as USART0 TX and PA8 as USART0 CTS */
36          pinmux = <PA6A_USART0_TXD0>, <PA8A_USART0_CTS0>;
37        };
38        /* group 2 */
39        group2 {
40          /* configure PA5 as USART0 RX and PA7 as USART0 RTS */
41          pinmux = <PA5A_USART0_RXD0>, <PA7A_USART0_RTS0>;
42          /* both PA5 and PA7 have pull-up enabled */
43          bias-pull-up;
44        };
45      };
46    };
47
48  The 'usart0_default' child node encodes the pin configurations for a
49  particular state of a device; in this case, the default (that is, active)
50  state.
51
52  As shown, pin configurations are organized in groups within each child node.
53  Each group can specify a list of pin function selections in the 'pinmux'
54  property.
55
56  A group can also specify shared pin properties common to all the specified
57  pins, such as the 'bias-pull-up' property in group 2. Here is a list of
58  supported standard pin properties:
59
60  - bias-pull-up: Enable pull-up resistor.
61  - bias-pull-down: Enable pull-down resistor.
62  - drive-open-drain: Open-drain drive mode.
63
64  To link pin configurations with a device, use a pinctrl-N property for some
65  number N, like this example you could place in your board's DTS file:
66
67    #include "board-pinctrl.dtsi"
68
69    &usart0 {
70          pinctrl-0 = <&usart0_default>;
71          pinctrl-names = "default";
72    };
73
74compatible: "atmel,sam-pinctrl"
75
76include: base.yaml
77
78properties:
79  "#address-cells":
80    required: true
81    const: 1
82  "#size-cells":
83    required: true
84    const: 1
85
86child-binding:
87  description: |
88    Each child node defines the configuration for a particular state.
89  child-binding:
90    description: |
91      The grandchild nodes group pins that share the same pin configuration.
92
93    include:
94      - name: pincfg-node.yaml
95        property-allowlist:
96          - bias-pull-up
97          - bias-pull-down
98          - drive-open-drain
99
100    properties:
101      pinmux:
102        required: true
103        type: array
104        description: |
105          An array of pins sharing the same group properties. The pins should
106          be defined using pre-defined macros or, alternatively, using the
107          SAM_PINMUX utility macros depending on the pinmux model used by the
108          SoC series.
109