| /Zephyr-latest/include/zephyr/drivers/pcie/ |
| D | msi.h | 11 * @brief PCIe Host MSI Interface
12 * @defgroup pcie_host_msi_interface PCIe Host MSI Interface
65 * @brief Allocate vector(s) for the endpoint MSI message(s)
68 * @param priority the MSI vectors base interrupt priority
69 * @param vectors an array for storing allocated MSI vectors
70 * @param n_vector the size of the MSI vectors array
72 * @return the number of allocated MSI vectors.
80 * @brief Connect the MSI vector to the handler
83 * @param vector the MSI vector to connect
99 * @brief Compute the target address for an MSI posted write.
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| /Zephyr-latest/dts/bindings/clock/ |
| D | st,stm32-msi-clock.yaml | 4 description: STM32 MSI Clock
6 compatible: "st,stm32-msi-clock"
11 msi-range:
16 MSI clock ranges
31 msi-pll-mode:
34 MSI clock PLL enable
35 Enables the PLL part of the MSI clock source.
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| D | st,stm32l0-msi-clock.yaml | 6 compatible: "st,stm32l0-msi-clock"
9 - name: st,stm32-msi-clock.yaml
11 - msi-range
14 msi-range:
19 MSI clock ranges
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| D | st,stm32u5-msi-clock.yaml | 6 compatible: "st,stm32u5-msi-clock"
9 - name: st,stm32-msi-clock.yaml
11 - msi-range
15 msi-range:
20 MSI clock ranges
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| /Zephyr-latest/drivers/pcie/host/ |
| D | Kconfig | 41 bool "Support for PCI(e) MSI"
44 enabled, PCI(e) devices which support MSI will be configured (at
51 bool "MSI multi-vector support"
53 MSI can support up to 32 different messages. This will enable the
61 bool "MSI-X support"
63 If one or more device support MSI-X, you'll need to enable this.
64 If a device exposes support for both MSI-X and MSI, MSI-X will be
65 used and MSI disabled on that device. Enable PCIE_MSI_MULTI_VECTOR
66 if you want to support multi-vector on MSI-X as well.
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| D | msi.c | 8 #include <zephyr/drivers/pcie/msi.h>
11 /* functions documented in include/drivers/pcie/msi.h */
13 static uint32_t pcie_msi_base(pcie_bdf_t bdf, bool *msi) in pcie_msi_base() argument
17 if (msi != NULL) { in pcie_msi_base()
18 *msi = true; in pcie_msi_base()
30 if (msi != NULL) { in pcie_msi_base()
31 *msi = false; in pcie_msi_base()
146 bool msi; in pcie_msi_vectors_allocate() local
148 base = pcie_msi_base(bdf, &msi); in pcie_msi_vectors_allocate()
151 set_msix(vectors, n_vector, !msi); in pcie_msi_vectors_allocate()
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| D | shell.c | 12 #include <zephyr/drivers/pcie/msi.h>
42 { PCI_CAP_ID_MSIX, "MSI-X" },
96 uint32_t msi; in show_msi() local
99 msi = pcie_get_cap(bdf, PCI_CAP_ID_MSI); in show_msi()
101 if (msi) { in show_msi()
102 data = pcie_conf_read(bdf, msi + PCIE_MSI_MCR); in show_msi()
103 shell_fprintf(sh, SHELL_NORMAL, " MSI support%s%s\n", in show_msi()
109 msi = pcie_get_cap(bdf, PCI_CAP_ID_MSIX); in show_msi()
111 if (msi) { in show_msi()
115 data = pcie_conf_read(bdf, msi + PCIE_MSIX_MCR); in show_msi()
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| D | CMakeLists.txt | 6 zephyr_library_sources_ifdef(CONFIG_PCIE_MSI msi.c)
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| /Zephyr-latest/drivers/interrupt_controller/ |
| D | Kconfig.intel_vtd | 14 technology. It's being used, currently, only for MSI/MSI-X
36 other device that would require it for MSI/MSI-X multi-vector support.
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| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/boards/ |
| D | core_init.overlay | 33 /delete-property/ msi-range;
34 /delete-property/ msi-pll-mode;
39 /delete-property/ msi-range;
40 /delete-property/ msi-pll-mode;
78 msi-range = <4>;
79 msi-pll-mode;
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| D | spi1_msik.overlay | 13 msi-range = <4>;
14 msi-pll-mode;
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| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/boards/ |
| D | clear_msi.overlay | 8 * Warning: This overlay clears the msi clock back to a state equivalent to what could
14 /delete-property/ msi-range;
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| D | pll_48_msi_4.overlay | 10 * It applies to the stm32xx where the msi is 4MHz
15 msi-range = <6>; /* default value */
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| D | wb_pll_48_msi_4.overlay | 10 * It applies to the stm32wb where the msi is 4MHz
15 msi-range = <6>; /* default value */
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| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/boards/ |
| D | msis_24.overlay | 18 msi-range = <1>;
19 msi-pll-mode;
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| D | msis_48.overlay | 18 msi-range = <0>;
19 msi-pll-mode;
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| D | pll_msis_160.overlay | 18 msi-range = <4>;
19 msi-pll-mode;
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| D | pll_msis_ahb_2_40.overlay | 18 msi-range = <4>;
19 msi-pll-mode;
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| D | clear_clocks.overlay | 28 /delete-property/ msi-range;
29 /delete-property/ msi-pll-mode;
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| /Zephyr-latest/drivers/virtualization/ |
| D | Kconfig | 40 MSI-X vector holders must be pre-allocated. One can pre-allocate
46 int "MSI-X interrupt priority"
50 Interrupt priority used for the MSI-X generated interrupts.
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| /Zephyr-latest/include/zephyr/drivers/interrupt_controller/ |
| D | intel_vtd.h | 9 #include <zephyr/drivers/pcie/msi.h>
43 bool msi);
81 * @brief Generate the MSI Message Address data for the given vector
84 * @param vector A valid allocated MSI vector array
87 * @return The MSI Message Address value
213 bool msi) in vtd_set_irte_msi() argument
218 api->set_irte_msi(dev, irte_idx, msi); in vtd_set_irte_msi()
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| /Zephyr-latest/drivers/disk/nvme/ |
| D | Kconfig | 11 driver to support these. It will enable MSI-X and MSI multi-vector
77 Interrupt priority used for the MSI-X generated interrupts.
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| /Zephyr-latest/drivers/pcie/endpoint/ |
| D | pcie_ep_iproc_msi.c | 23 * MSI-X Table offset 0x10000 on BAR2, in iproc_pcie_msix_config()
24 * MSI-X PBA offset 0x10800 on BAR2. in iproc_pcie_msix_config()
57 * from device before host driver sets up MSI. in iproc_pcie_generate_msi()
60 LOG_WRN("MSI is not setup, skipping MSI"); in iproc_pcie_generate_msi()
213 LOG_WRN("Exceeded max supported MSI-X (%d)", MSIX_TABLE_SIZE); in iproc_pcie_generate_msix()
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| D | Kconfig.iproc | 14 bool "Re-initialize PCIe MSI/MSIX configurations"
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| /Zephyr-latest/dts/bindings/rng/ |
| D | st,stm32-rng.yaml | 19 <&rcc STM32_SRC_MSI CLK48_SEL(3)> /* RNG clock domain set to MSI */
22 In the provided example, MSI should be configured to provide 48Mhz clock.
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