Searched full:mosi (Results 1 – 25 of 286) sorted by relevance
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| /Zephyr-latest/dts/bindings/spi/ |
| D | zephyr,spi-bitbang.yaml | 17 mosi-gpios:
20 MOSI gpio info. Output pin for Master Out Slave In.
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| D | espressif,esp32-spi.yaml | 33 Use MOSI for both sending and receiving data
83 Default MISO and MOSI pins GPIO level when idle. Defaults to high by default.
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| D | microchip,xec-qmspi-ldma.yaml | 40 MOSI and MISO or half-duplex on MOSI only. Lines set to 2
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| /Zephyr-latest/drivers/spi/ |
| D | spi_bitbang.c | 79 const struct gpio_dt_spec *mosi = NULL; in spi_bitbang_transceive() local
89 LOG_ERR("No MOSI pin specified in half duplex mode"); in spi_bitbang_transceive()
98 mosi = &info->mosi_gpio; in spi_bitbang_transceive()
106 mosi = &info->mosi_gpio; in spi_bitbang_transceive()
117 LOG_ERR("Couldn't configure MOSI pin: %d", rc); in spi_bitbang_transceive()
179 if (mosi) { in spi_bitbang_transceive()
180 gpio_pin_set_dt(mosi, d); in spi_bitbang_transceive()
285 LOG_ERR("GPIO port for mosi pin is not ready"); in spi_bitbang_init()
291 LOG_ERR("Couldn't configure mosi pin; (%d)", rc); in spi_bitbang_init()
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| /Zephyr-latest/tests/drivers/spi/spi_controller_peripheral/boards/ |
| D | ek_ra8m1.overlay | 9 /* MISO MOSI RSPCK SSL */
18 /* MISO MOSI RSPCK SSL */
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| /Zephyr-latest/dts/bindings/gpio/ |
| D | mikro-bus.yaml | 15 numbered 0 - 5 (AN - MOSI), the right side pins are numbered 6 - 10
24 SPI Master Output Slave Input - MOSI SDA - I2C Data
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| D | atmel-xplained-header.yaml | 22 Px5 MOSI
39 4 SPI(CS0) 5 6 SPI(MOSI) 5
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| D | m5stack,atom-header.yaml | 11 2 GPIO/MOSI 3 GPIO/DAC0/SDA
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| D | m5stack,mbus-header.yaml | 12 6 MOSI 7 DAC0
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| /Zephyr-latest/boards/google/dragonclaw/doc/ |
| D | index.rst | 23 - SPI_1 CS/CLK/MISO/MOSI : PA4/PA5/PA6/PA7
24 - SPI_2 CS/CLK/MISO/MOSI : PB12/PB13/PB14/PB15
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| /Zephyr-latest/boards/google/icetower/doc/ |
| D | index.rst | 23 - SPI_1 CS/CLK/MISO/MOSI : PA4/PA5/PA6/PA7
24 - SPI_4 CS/CLK/MISO/MOSI : PE11/PE12/PE13/PE14
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| /Zephyr-latest/boards/telink/tlsr9518adk80d/ |
| D | tlsr9518adk80d-pinctrl.dtsi | 39 /* PSPI: CLK(PC5), MOSI(PC7), MISO(PC6) */
51 /* HSPI: CLK(PA2), MOSI(PA4), MISO(PA3) */
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| /Zephyr-latest/tests/drivers/gpio/gpio_basic_api/boards/ |
| D | mr_canhubk3.overlay | 10 /* Use LPSPI1 MISO/MOSI pins which are also used for spi_loopback test */
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| D | mr_canhubk3_wkpu.overlay | 12 /* Use LPSPI1 MISO/MOSI pins which are also used for spi_loopback test */
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| /Zephyr-latest/tests/drivers/spi/spi_loopback/boards/ |
| D | intel_adl_crb.overlay | 7 /* External Loopback: Short MOSI & MISO */
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| D | ucans32k1sic.overlay | 7 /* Short P1.3 (SPI0/MISO) with P1.4 (SPI0/MOSI) */
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| D | frdm_mcxn236.overlay | 8 * LPSPI3 MOSI(J2-8, P1_0/FC3_P0) --> LPSPI5 MISO(J2-10, P1_2/FC3_P2)
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| D | intel_rpl_p_crb.overlay | 7 /* External Loopback: Short MOSI & MISO */
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| D | samd21_xpro.overlay | 8 /* Internally connect MOSI to MISO for loop-back operation */
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| D | samr21_xpro.overlay | 8 /* Internally connect MOSI to MISO for loop-back operation */
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| D | intel_rpl_s_crb.overlay | 7 /* External Loopback: Short MOSI (J7H4.3) & MISO (J7H4.5) */
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| /Zephyr-latest/samples/drivers/spi_bitbang/boards/ |
| D | nrf52840dk_nrf52840.overlay | 14 mosi-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
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| /Zephyr-latest/samples/boards/nordic/nrfx_prs/ |
| D | README.rst | 30 board (between the MOSI and MISO pins for SPIMs and between the TX and RX pins
35 on the boards supported by the sample are assigned as MOSI/MISO and TX/RX pins.
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| /Zephyr-latest/drivers/led_strip/ |
| D | Kconfig.lpd880x | 17 reduced SPI interface (MOSI and CLK lines only).
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| /Zephyr-latest/boards/arm/mps2/ |
| D | pinmux.c | 129 | (1<<13) /* Shield 0 SPI 3 MOSI */ in arm_mps2_pinmux_defaults()
139 | (1<<2) /* ADC SPI 2 MOSI */ in arm_mps2_pinmux_defaults()
148 | (1<<7) /* Shield 1 SPI 4 MOSI */ in arm_mps2_pinmux_defaults()
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