Searched full:mips (Results 1 – 25 of 51) sorted by relevance
123
6 bool "MIPS CP0 Timer"7 depends on MIPS10 This module implements a kernel device driver for the MIPS CP0 timer.
9 menu "MIPS Options"10 depends on MIPS14 default "mips"
1 .. _boards-mips:3 MIPS Boards
6 bool "MIPS Qemu Malta implementation"7 select MIPS
19 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/mips/linker.ld CACHE INTERNAL "")
8 #include <mips/regdef.h>
2 name: QEMU emulation for MIPS (little endian)5 arch: mips
2 name: QEMU emulation for MIPS (big endian)5 arch: mips
8 bool "QEMU emulation for little endian MIPS Malta"13 bool "QEMU emulation for big endian MIPS Malta"
9 # mips13 - mips
3 MIPS Malta Emulation (QEMU)9 This board configuration will use QEMU to emulate the MIPS Malta platform.11 This configuration provides support for an MIPS 4Kc/24Kc CPU cores and these devices:20 with an actual MIPS Malta hardware system, or any other hardware system.49 see target/mips/cp0_timer.c in Qemu source tree for details.106 https://www.linux-mips.org/wiki/MIPS_Malta
14 - mips27 - mips
9 - mips33 - mips
12 #include <zephyr/arch/mips/thread.h>13 #include <zephyr/arch/mips/exception.h>21 #include <mips/mipsregs.h>
9 #include <mips/regdef.h>10 #include <mips/mipsregs.h>
12 #include <mips/regdef.h>
4 * Macros for MIPS CP0 registers manipulations5 * inspired by linux/arch/mips/include/asm/mipsregs.h
52 - mips68 - mips
15 - mips
5 description: MIPS CPU interrupt controller
22 mips/index.rst
14 * other definitions for the MIPS processor architecture.
8 - mips
17 - mips
