Searched full:mio_pin_xx (Results 1 – 3 of 3) sorted by relevance
144 L3_SEL, L2_SEL, L1_SEL, and L0_SEL fields in the MIO_PIN_xx SLCR register.148 Disable any IO buffer pin bias. Clears the PULLUP and TRI_ENABLE fields in the MIO_PIN_xx153 Enables tri-state on IO buffer pin. Sets the TRI_ENABLE field in the MIO_PIN_xx SLCR158 Enables pull-up on IO buffer pin. Sets the PULLUP field in the MIO_PIN_xx SLCR register.163 power-source (IO_Type) is HSTL. Sets the DisableRcvr field in the MIO_PIN_xx SLCR169 DisableRcvr field in the MIO_PIN_xx SLCR register.174 IO buffer type. Sets the IO_Type field in the MIO_PIN_xx SLCR register. The IO_STANDARD_*186 LVCMOS33. Sets the Speed field in the MIO_PIN_xx SLCR register. The IO_SPEED_* macros are
14 * corresponds to what is written to the IO_Type field in the MIO_PIN_xx SLCR register.28 * corresponds to what is written to the Speed field in the MIO_PIN_xx SLCR register.
18 /* MIO_PIN_xx SLCR register fields (from Xilinx UG585 v1.13, B.28 SLCR) */46 /* MIO_PIN_xx SLCR register L3..L0 multiplexing fields combined */
