Searched full:mii (Results 1 – 25 of 31) sorted by relevance
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| /Zephyr-Core-3.5.0/dts/bindings/dsa/ |
| D | microchip,ksz8794.yaml | 19 mii-lowspeed-drivestrength:
22 Define the Low-Speed Interface Drive Strength for MII and RMMI
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| /Zephyr-Core-3.5.0/drivers/ethernet/phy/ |
| D | Kconfig | 25 bool "Generic MII PHY Driver"
30 This is a generic MII PHY interface that communicates with the
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| D | phy_mii.c | 16 #include <zephyr/net/mii.h>
167 LOG_DBG("PHY (%d) Starting MII PHY auto-negotiate sequence", in update_link_state()
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| D | phy_adin2111.c | 20 #include <zephyr/net/mii.h>
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| /Zephyr-Core-3.5.0/drivers/ethernet/ |
| D | eth_smsc91x_priv.h | 130 #define MD_INT 0x0080 /* MII */
134 #define MGMT_MDO 0x0001 /* MII management output */
135 #define MGMT_MDI 0x0002 /* MII management input */
136 #define MGMT_MCLK 0x0004 /* MII management clock */
137 #define MGMT_MDOE 0x0008 /* MII management output enable */
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| D | phy_cyclonev.c | 108 /* Prepare the MII address register value */ in alt_eth_phy_write_register()
118 /* Set the MII Busy bit */ in alt_eth_phy_write_register()
121 /* Give the value to the MII data register */ in alt_eth_phy_write_register()
123 /* Write the result value into the MII Address register */ in alt_eth_phy_write_register()
155 /* Prepare the MII address register value */ in alt_eth_phy_read_register()
165 /* Set the MII Busy bit */ in alt_eth_phy_read_register()
168 /* Write the result value into the MII Address register */ in alt_eth_phy_read_register()
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| D | Kconfig.nxp_s32_gmac | 82 internal FIFO on to the internal MII/GMII interface, passing through
84 This mode requires the MII/GMII Rx clock input signal to function
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| D | Kconfig.stm32_hal | 120 bool "Use MII interface"
122 Use the MII physical interface instead of RMII.
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| D | eth_esp32.c | 217 /* Configure phy for Media-Independent Interface (MII) or in eth_esp32_initialize()
226 } else if (strcmp(phy_connection_type, "mii") == 0) { in eth_esp32_initialize()
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| D | eth_enc28j60_priv.h | 25 * 0x2 MII Register
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| D | phy_gecko.c | 12 #include <zephyr/net/mii.h>
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| D | eth_cyclonev_priv.h | 248 #define EMAC_GMACGRP_MAC_CONFIGURATION_PS_SET_MSK 0x00008000 /* Port Select = MII */
379 /*!< Receive error: error reported by MII interface */
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| D | eth_smsc91x.c | 25 * MII
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| D | eth_xlnx_gem_priv.h | 255 * [11] Use TBI instead of the GMII/MII interface
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| /Zephyr-Core-3.5.0/include/zephyr/net/ |
| D | mii.h | 9 * @brief Definitions for IEEE 802.3, Section 2 MII compatible PHY transceivers
16 * @brief Ethernet MII (media independent interface) functions
17 * @defgroup ethernet_mii Ethernet MII Support Functions
22 /* MII management registers */
63 /** isolate electrically PHY from MII */
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| /Zephyr-Core-3.5.0/dts/bindings/ethernet/ |
| D | espressif,esp32-eth.yaml | 16 - "mii"
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| D | nxp,s32-gmac.yaml | 23 - "mii"
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| D | ethernet-phy.yaml | 6 description: Generic MII PHY
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| D | atmel,gmac-common.yaml | 50 - "mii"
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| D | xlnx,gem.yaml | 282 bled instead of the GMII/MII interface.
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| /Zephyr-Core-3.5.0/dts/arm/atmel/ |
| D | sam4e.dtsi | 167 phy-connection-type = "mii";
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| /Zephyr-Core-3.5.0/boards/arm/ip_k66f/doc/ |
| D | index.rst | 11 Ethernet switch with Gigabit RGMII/MII/RMII interface.
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| /Zephyr-Core-3.5.0/boards/arm/stm32f769i_disco/doc/ |
| D | index.rst | 82 - 10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII
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| /Zephyr-Core-3.5.0/boards/arm/96b_avenger96/doc/ |
| D | index.rst | 103 - 10/100M or Gigabit Ethernet GMAC (IEEE 1588v2 hardware, MII/RMII/GMII/RGMI)
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| /Zephyr-Core-3.5.0/boards/arm/stm32mp157c_dk2/doc/ |
| D | stm32mp157_dk2.rst | 113 - 10/100M or Gigabit Ethernet GMAC (IEEE 1588v2 hardware, MII/RMII/GMII/RGMI)
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