| /Zephyr-Core-2.7.6/lib/libc/minimal/source/stdlib/ |
| D | qsort.c | 15 * Normally parent is defined parent(k) = floor((k-1) / 2) but we can avoid a
16 * divide by noticing that floor((k-1) / 2) = ((k - 1) >> 1).
19 #define parent(k) (((k) - 1) >> 1) argument
21 * Normally left is defined left(k) = (2 * k + 1) but we can avoid a
22 * multiply by noticing that (2 * k + 1) = ((k << 1) + 1).
25 #define left(k) (((k) << 1) + 1) argument
28 * Normally right is defined right(k) = (2 * k + 2) but we can avoid a
29 * multiply by noticing that right(k) = left(k) + 1
31 #define right(k) (left(k) + 1) argument
33 #define A(k) ((uint8_t *)base + size * (k)) argument
|
| /Zephyr-Core-2.7.6/dts/bindings/pwm/ |
| D | telink,b91-pwm.yaml | 20 description: Default PWM Peripheral Clock frequency in Hz (is used if 32K Clock is disabled)
25 description: Enable 32K Source Clock for PWM Channel 0
30 description: Enable 32K Source Clock for PWM Channel 1
35 description: Enable 32K Source Clock for PWM Channel 2
40 description: Enable 32K Source Clock for PWM Channel 3
45 description: Enable 32K Source Clock for PWM Channel 4
50 description: Enable 32K Source Clock for PWM Channel 5
|
| /Zephyr-Core-2.7.6/samples/net/zperf/ |
| D | README.rst | 54 $ iperf -s -l 1K -u -V -B 2001:db8::2
60 $ iperf -s -l 1K -V -B 2001:db8::2
67 zperf udp upload 2001:db8::2 5001 10 1K 1M
74 zperf tcp upload 2001:db8::2 5001 10 1K 1M
82 zperf udp upload2 v6 10 1K 1M
89 zperf tcp upload2 v6 10 1K 1M
111 $ iperf -l 1K -u -V -c 2001:db8::1 -p 5001
118 $ iperf -l 1K -V -c 2001:db8::1 -p 5001
|
| /Zephyr-Core-2.7.6/samples/sensor/max6675/ |
| D | README.rst | 1 MAX6675 K-thermocouple to digital converter
8 cold-junction-compensated K-thermocouple to digital converter.
14 - K-thermocouple connected to MAX6675 T+/T- inputs
37 temperature fetch will fail if the K-thermocouple is not connected. This is
38 because MAX6675 is able to detect if the K-thermocouple is connected or not.
|
| /Zephyr-Core-2.7.6/soc/arm/nxp_imx/rt/ |
| D | Kconfig.defconfig.series | 90 default $(dt_node_reg_size_int,/memory@80000000,0,K)
100 default $(dt_node_reg_size_int,/soc/flexram@40028000/itcm@0,0,K) if SOC_SERIES_IMX_RT11XX
101 default $(dt_node_reg_size_int,/soc/flexram@400b0000/itcm@0,0,K) if SOC_SERIES_IMX_RT10XX
112 default $(dt_node_reg_size_int,/soc/memory@1ffe0000,0,K)
123 default $(dt_node_reg_size_int,/soc/spi@400cc000,1,K) if SOC_SERIES_IMX_RT11XX
124 default $(dt_node_reg_size_int,/soc/spi@402a8000,1,K) if SOC_SERIES_IMX_RT10XX
135 default $(dt_node_reg_size_int,/soc/spi@4000d000,1,K) if SOC_SERIES_IMX_RT11XX
136 default $(dt_node_reg_size_int,/soc/spi@402a4000,1,K) if SOC_SERIES_IMX_RT10XX
|
| /Zephyr-Core-2.7.6/arch/arc/core/mpu/ |
| D | arc_mpu_v2_internal.h | 18 * 0x8 512 0x9 1k 0xA 2K 0xB 4K
19 * 0xC 8K 0xD 16K 0xE 32K 0xF 64K
20 * 0x10 128K 0x11 256K 0x12 512K 0x13 1M
|
| D | arc_mpu_v6_internal.h | 21 * 0x8 512 0x9 1k 0xA 2K 0xB 4K
22 * 0xC 8K 0xD 16K 0xE 32K 0xF 64K
23 * 0x10 128K 0x11 256K 0x12 512K 0x13 1M
|
| /Zephyr-Core-2.7.6/soc/arm/microchip_mec/mec172x/reg/ |
| D | mec172x_vbat.h | 33 /* Offset 0x08 32K Clock Source register */
59 /* 32K silicon OSC when chip powered by VBAT or VTR */
61 /* 32K external crystal when chip powered by VBAT or VTR */
63 /* 32K input pin on VTR. Switch to Silicon OSC on VBAT */
65 /* 32K input pin on VTR. Switch to crystal on VBAT */
67 /* Disable internal 32K VBAT clock source when VTR is off */
|
| /Zephyr-Core-2.7.6/subsys/net/ip/ |
| D | trickle.c | 29 return trickle->k == NET_TRICKLE_INFINITE_REDUNDANCY; in is_suppression_disabled()
35 (trickle->c < trickle->k); in is_tx_allowed()
111 NET_DBG("TX ok %d c(%u) < k(%u)", in inteval_timeout()
112 is_tx_allowed(trickle), trickle->c, trickle->k); in inteval_timeout()
162 uint8_t k) in net_trickle_create() argument
164 NET_ASSERT(trickle && Imax > 0 && k > 0 && !CHECK_IMIN(Imin)); in net_trickle_create()
171 trickle->k = k; in net_trickle_create()
175 NET_DBG("Imin %d Imax %u k %u Imax_abs %d", in net_trickle_create()
176 trickle->Imin, trickle->Imax, trickle->k, in net_trickle_create()
|
| /Zephyr-Core-2.7.6/soc/sparc/gr716a/ |
| D | linker.ld | 22 bootprom (rx) : ORIGIN = 0x00000000, LENGTH = 4K
26 RAM (rw) : ORIGIN = 0x30000000, LENGTH = 64K
27 SRAM (x) : ORIGIN = 0x31000000, LENGTH = 128K
30 IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K
|
| /Zephyr-Core-2.7.6/boards/arm/bl5340_dvk/ |
| D | bl5340_dvk_cpunet.dts | 69 /* 48K */
74 /* 88K */
79 /* 88K */
84 /* 12K */
89 /* 20K */
|
| /Zephyr-Core-2.7.6/samples/modules/tflite-micro/magic_wand/train/ |
| D | data_augmentation.py | 36 for k in range(denominator):
38 k][j] = (data[molecule * i + k][j] * (denominator - k) +
39 data[molecule * i + k + 1][j] * k) / denominator
|
| /Zephyr-Core-2.7.6/drivers/sensor/max6675/ |
| D | Kconfig | 5 bool "MAX6675 K-thermocouple to digital converter"
8 Enable MAX6675 cold-junction-compensated K-thermocouple to digital
|
| /Zephyr-Core-2.7.6/dts/bindings/flash_controller/ |
| D | st,stm32wb-flash-controller.yaml | 10 description: dual-bank mode not enabled (page erase 4096k)
15 description: dual-bank mode enabled (page erase 2048k)
|
| /Zephyr-Core-2.7.6/lib/os/ |
| D | p4wq.c | 78 k_spinlock_key_t k = k_spin_lock(&queue->lock); in p4wq_loop() local
93 k_spin_unlock(&queue->lock, k); in p4wq_loop()
97 k = k_spin_lock(&queue->lock); in p4wq_loop()
108 z_pend_curr(&queue->lock, k, &queue->waitq, K_FOREVER); in p4wq_loop()
109 k = k_spin_lock(&queue->lock); in p4wq_loop()
219 k_spinlock_key_t k = k_spin_lock(&queue->lock); in k_p4wq_submit() local
286 z_reschedule(&queue->lock, k); in k_p4wq_submit()
291 k_spin_unlock(&queue->lock, k); in k_p4wq_submit()
296 k_spinlock_key_t k = k_spin_lock(&queue->lock); in k_p4wq_cancel() local
304 k_spin_unlock(&queue->lock, k); in k_p4wq_cancel()
|
| /Zephyr-Core-2.7.6/boards/arm/bt510/ |
| D | bt510.dts | 141 /* 96K */
146 /* 396K */
151 /* 396K */
156 /* 8K */
171 /* 128K */
|
| /Zephyr-Core-2.7.6/samples/drivers/counter/maxim_ds3231/boards/ |
| D | particle_xenon.overlay | 7 &i2c0 { /* SDA P0.26, SCL P0.27, ISW P1.1, 32K P1.2 */
14 32k-gpios = <&gpio1 2 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
|
| /Zephyr-Core-2.7.6/tests/drivers/counter/maxim_ds3231_api/boards/ |
| D | particle_xenon.overlay | 7 &i2c0 { /* SDA P0.26, SCL P0.27, ISW P1.1, 32K P1.2 */
14 32k-gpios = <&gpio1 2 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
|
| /Zephyr-Core-2.7.6/boards/arm/stm32l1_disco/doc/ |
| D | index.rst | 19 - STM32LDISCOVERY targets STM32L152RBT6, with 128K flash, 16K RAM
20 - 32L152CDISCOVERY targets STM32L152RCT6, with 256K flash, 32K RAM
23 configuration assumes only 128K flash and 16K RAM, so it builds and runs
|
| /Zephyr-Core-2.7.6/subsys/net/lib/lwm2m/ |
| D | lwm2m_util.c | 181 int32_t f, k, i, e; in lwm2m_b32_to_f32() local
218 k = LWM2M_FLOAT32_DEC_MAX; in lwm2m_b32_to_f32()
222 k /= 2; in lwm2m_b32_to_f32()
227 k /= 2; in lwm2m_b32_to_f32()
229 f32->val2 += k; in lwm2m_b32_to_f32()
240 int64_t f, k; in lwm2m_b64_to_f32() local
282 k = LWM2M_FLOAT32_DEC_MAX; in lwm2m_b64_to_f32()
286 k /= 2; in lwm2m_b64_to_f32()
291 k /= 2; in lwm2m_b64_to_f32()
293 f32->val2 += k; in lwm2m_b64_to_f32()
|
| /Zephyr-Core-2.7.6/drivers/crypto/ |
| D | Kconfig.ataes132a | 7 bool "Atmel ATAES132A 32k AES Serial EEPROM support"
10 Enable Atmel ATAES132A 32k AES Serial EEPROM support.
|
| /Zephyr-Core-2.7.6/drivers/dma/ |
| D | dma_iproc_pax_v2.h | 53 * to make sure BD memories fall in 4K alignment.
58 * Per-ring memory, with 8K & 4K alignment
60 * s/w need to allocate extra upto 8K to
|
| D | dma_iproc_pax_v1.h | 36 /* ascii signature 'V' 'K' */
51 * Per-ring memory, with 8K & 4K alignment
53 * s/w need to allocate extra upto 8K to
|
| /Zephyr-Core-2.7.6/include/arch/arm/aarch32/cortex_a_r/scripts/ |
| D | linker.ld | 39 #define ROM_SIZE (CONFIG_FLASH_SIZE*1K - CONFIG_FLASH_LOAD_OFFSET)
44 #define RAM_SIZE (CONFIG_BOOTLOADER_SRAM_SIZE * 1K)
46 (CONFIG_SRAM_SIZE * 1K - RAM_SIZE))
48 #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K)
52 #define RAM_SIZE (CONFIG_SRAM_SIZE * 1K - CONFIG_BOOTLOADER_SRAM_SIZE * 1K)
80 IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K
200 * usually 4k aligned.
|
| /Zephyr-Core-2.7.6/kernel/ |
| D | smp.c | 107 unsigned int k = arch_irq_lock(); in z_smp_cpu_mobile() local
108 bool pinned = arch_is_in_isr() || !arch_irq_unlocked(k); in z_smp_cpu_mobile()
110 arch_irq_unlock(k); in z_smp_cpu_mobile()
|
