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/Zephyr-Core-3.5.0/drivers/serial/
Duart_ns16550.c232 #define IER(dev) (get_port(dev) + REG_IER * reg_interval(dev)) macro
581 ns16550_outbyte(dev_cfg, IER(dev), 0x00);
827 * @brief Enable TX interrupt in IER
857 ns16550_outbyte(dev_cfg, IER(dev), ns16550_inbyte(dev_cfg, IER(dev)) | IER_TBE);
863 * @brief Disable TX interrupt in IER
873 ns16550_outbyte(dev_cfg, IER(dev),
874 ns16550_inbyte(dev_cfg, IER(dev)) & (~IER_TBE));
940 * @brief Enable RX interrupt in IER
950 ns16550_outbyte(dev_cfg, IER(dev), ns16550_inbyte(dev_cfg, IER(dev)) | IER_RXRDY);
956 * @brief Disable RX interrupt in IER
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Duart_lpc11u6x.c229 cfg->uart0->ier = (cfg->uart0->ier & LPC11U6X_UART0_IER_MASK) | in lpc11u6x_uart0_irq_tx_enable()
233 * enabling it in the IER register. We have to trigger it. in lpc11u6x_uart0_irq_tx_enable()
242 cfg->uart0->ier = (cfg->uart0->ier & LPC11U6X_UART0_IER_MASK) & in lpc11u6x_uart0_irq_tx_disable()
258 (cfg->uart0->ier & LPC11U6X_UART0_IER_THREINTEN); in lpc11u6x_uart0_irq_tx_ready()
265 cfg->uart0->ier = (cfg->uart0->ier & LPC11U6X_UART0_IER_MASK) | in lpc11u6x_uart0_irq_rx_enable()
273 cfg->uart0->ier = (cfg->uart0->ier & LPC11U6X_UART0_IER_MASK) & in lpc11u6x_uart0_irq_rx_disable()
291 cfg->uart0->ier = (cfg->uart0->ier & LPC11U6X_UART0_IER_MASK) | in lpc11u6x_uart0_irq_err_enable()
299 cfg->uart0->ier = (cfg->uart0->ier & LPC11U6X_UART0_IER_MASK) & in lpc11u6x_uart0_irq_err_disable()
DKconfig.ns1655083 bool "Re-enable interrupts by toggling IER at end of ISR"
93 the IER is being toggled to re-assert interrupts at the end of ISR
Duart_mchp_xec.c309 regs->IER = (unsigned char)((divisor >> 8) & 0x7f); in set_baud_rate()
418 regs->IER = 0; in uart_xec_configure()
686 * @brief Enable TX interrupt in IER
697 regs->IER |= IER_TBE; in uart_xec_irq_tx_enable()
703 * @brief Disable TX interrupt in IER
714 regs->IER &= ~(IER_TBE); in uart_xec_irq_tx_disable()
761 * @brief Enable RX interrupt in IER
772 regs->IER |= IER_RXRDY; in uart_xec_irq_rx_enable()
778 * @brief Disable RX interrupt in IER
789 regs->IER &= ~(IER_RXRDY); in uart_xec_irq_rx_disable()
[all …]
Duart_altera_jtag.c277 * @brief Enable TX interrupt in IER
296 * @brief Disable TX interrupt in IER
375 * @brief Enable RX interrupt in IER
394 * @brief Disable RX interrupt in IER
Duart_stellaris.c401 * @brief Disable TX interrupt in IER
427 * @brief Enable RX interrupt in IER
439 * @brief Disable RX interrupt in IER
Duart_xlnx_ps.c886 * @brief Enable TX interrupt in IER
900 * @brief Disable TX interrupt in IER
952 * @brief Enable RX interrupt in IER
964 * @brief Disable RX interrupt in IER
996 * @brief Enable error interrupt in IER
1014 * @brief Disable error interrupt in IER
Duart_cdns.h64 /* @brief IER, IDR, IMR and CSIR Registers offset 0x08, 0xC, 0x10 and 0x14 */
Duart_lpc11u6x.h101 volatile uint32_t ier; /* Interrupt enable */ member
/Zephyr-Core-3.5.0/dts/bindings/spi/
Dst,stm32h7-spi.yaml9 presence of a dedicated interrupt enable register (IER).
/Zephyr-Core-3.5.0/soc/riscv/riscv-ite/common/
Dsoc_common_irq.c32 * bit, and SOC's IER are both true. in arch_irq_is_enabled()
/Zephyr-Core-3.5.0/soc/riscv/openisa_rv32m1/
Dsoc.c114 uint32_t channel, line, ier; in arch_irq_is_enabled() local
125 ier = INTMUX->CHANNEL[channel].CHn_IER_31_0 & BIT(line); in arch_irq_is_enabled()
127 return ier != 0U; in arch_irq_is_enabled()
/Zephyr-Core-3.5.0/drivers/can/
Dcan_stm32_bxcan.c710 can->IER |= CAN_IER_TMEIE; in can_stm32_init()
727 can->IER &= ~(CAN_IER_BOFIE | CAN_IER_EPVIE | CAN_IER_EWGIE); in can_stm32_set_state_change_callback()
729 can->IER |= CAN_IER_BOFIE | CAN_IER_EPVIE | CAN_IER_EWGIE; in can_stm32_set_state_change_callback()
1133 can->IER |= CAN_IER_TMEIE | CAN_IER_ERRIE | CAN_IER_FMPIE0 | \
1136 can->IER |= CAN_IER_LECIE; \
1156 can->IER |= CAN_IER_TMEIE | CAN_IER_ERRIE | CAN_IER_FMPIE0 | \
1159 can->IER |= CAN_IER_LECIE; \
Dcan_sja1000_priv.h84 /* Interrupt Enable Register (IER) bits */
/Zephyr-Core-3.5.0/drivers/ethernet/
Deth_sam0_gmac.h24 #define GMAC_IER IER.reg
Deth_xlnx_gem_priv.h161 * IER = gem.intr_en Interrupt enable register
Deth_sam_gmac.c1687 LOG_DBG("IER HRESP"); in queue0_isr()
/Zephyr-Core-3.5.0/soc/arm/microchip_mec/common/reg/
Dmec_uart.h167 volatile uint8_t IER; member
/Zephyr-Core-3.5.0/drivers/i2c/
Di2c_sam4l_twim.c374 twim->IER = TWIM_IER_STD_MASK | in i2c_start_xfer()
403 twim->IER |= (cur_is_read ? TWIM_IER_RXRDY : TWIM_IER_TXRDY); in i2c_prepare_next()
Di2c_xilinx_axi.c278 LOG_DBG("Set IER to 0x%02x", int_enable); in i2c_xilinx_axi_wait_interrupt()
/Zephyr-Core-3.5.0/drivers/timer/
Dstm32_lptim_timer.c318 /* Wait for the IER register of the stm32U5 ready, after any bit write operation */
/Zephyr-Core-3.5.0/include/zephyr/drivers/
Duart.h859 * @brief Enable TX interrupt in IER.
880 * @brief Disable TX interrupt in IER.