Searched full:idr (Results 1 – 14 of 14) sorted by relevance
138 * ext_data parameters are passed using the IDR/IDD registers.145 * @param data 30 bits value to transmit with the message (IDR register).159 * @param data 30 bits value to transmit with the message (IDR register)171 * using the IDR/IDD registers. Waits in a loop until it is possible to send a message.174 * @param data 30 bits value to transmit with the message (IDR register).
26 uint32_t idr; member47 * This clears BUSY on the other side of the connection in IDR register.
26 uint32_t idr; member44 * This clears BUSY on the other side of the connection in IDR register.
18 uint32_t idr; member
136 bool not_busy = (config->regs->idr & INTEL_ADSP_IPC_BUSY) == 0; in intel_adsp_ipc_is_complete()158 if ((config->regs->idr & INTEL_ADSP_IPC_BUSY) != 0 || devdata->tx_ack_pending) { in intel_adsp_ipc_send_message()168 config->regs->idr = data | INTEL_ADSP_IPC_BUSY; in intel_adsp_ipc_send_message()197 while (regs->idr & INTEL_ADSP_IPC_BUSY) { in intel_adsp_ipc_send_message_emergency()211 regs->idr = data | INTEL_ADSP_IPC_BUSY; in intel_adsp_ipc_send_message_emergency()
41 Enable and select LPF cutoff frequency for a given IDR (Input Data Rate).59 This helps in producing slower Output Data Rate (ODR) from given Input Data Rate (IDR).
48 message are passed in the cAVS IDR/TDR register pair instead
66 /* cAVS IDR register has only 30 usable bits */ in send()142 /* 30 user-writable bits in cAVS IDR register */ in max_id_val_get()
297 twim->IDR = ~0UL; /* Clear the interrupt flags */ in i2c_start_xfer()454 twim->IDR = TWIM_IDR_RXRDY; in i2c_sam_twim_isr()474 twim->IDR = TWIM_IDR_TXRDY; in i2c_sam_twim_isr()493 twim->IDR = ~0UL; in i2c_sam_twim_isr()
25 #define GMAC_IDR IDR.reg
162 * IDR = gem.intr_dis Interrupt disable register
64 /* @brief IER, IDR, IMR and CSIR Registers offset 0x08, 0xC, 0x10 and 0x14 */
232 IDC[core].agents[1].ipc.idr = msg | INTEL_ADSP_IPC_BUSY; in send_ipi()
