| /Zephyr-Core-3.7.0/subsys/tracing/ctf/tsdl/ |
| D | metadata | 12 uint8_t id;
27 id = 0x10;
36 id = 0x11;
45 id = 0x12;
56 id = 0x13;
65 id = 0x14;
74 id = 0x15;
83 id = 0x16;
91 id = 0x17;
100 id = 0x18;
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| /Zephyr-Core-3.7.0/doc/services/input/ |
| D | diodes-cr.svg | 7 id="svg3728"
11 id="defs3732" />
13 …id="title2">SVG Image created as keyboard-matrix-testboard-diodes-cr.svg date 2023/12/18 09:58:32 …
15 id="desc4">Image generated by Eeschema-SVG </desc>
18 id="g6"
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| D | diodes-rc.svg | 7 id="svg3728"
11 id="defs3732" />
13 …id="title2">SVG Image created as keyboard-matrix-testboard-diodes-rc.svg date 2023/12/18 09:58:32 …
15 id="desc4">Image generated by Eeschema-SVG </desc>
18 id="g6"
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26 id="g10"
30 id="g12"
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| D | no-diodes.svg | 7 id="svg1632"
11 id="defs1636" />
13 …id="title2">SVG Image created as keyboard-matrix-testboard-no-diodes.svg date 2023/12/18 09:58:32 …
15 id="desc4">Image generated by Eeschema-SVG </desc>
18 id="g6"
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| D | no-sw4.svg | 7 id="svg1516"
11 id="defs1520" />
13 …id="title2">SVG Image created as keyboard-matrix-testboard-no-sw4.svg date 2023/12/18 09:58:32 </t…
15 id="desc4">Image generated by Eeschema-SVG </desc>
18 id="g6"
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| /Zephyr-Core-3.7.0/scripts/build/ |
| D | uf2families.json | 3 "id": "0x16573617", string
8 "id": "0x1851780a", string
13 "id": "0x1b57745f", string
18 "id": "0x1c5f21b0", string
23 "id": "0x1e1f432d", string
28 "id": "0x202e3a91", string
33 "id": "0x21460ff0", string
38 "id": "0x2abc77ec", string
43 "id": "0x300f5633", string
48 "id": "0x31d228c6", string
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| /Zephyr-Core-3.7.0/drivers/dma/ |
| D | dma_stm32_v1.c | 20 uint32_t dma_stm32_id_to_stream(uint32_t id) in dma_stm32_id_to_stream() argument
33 __ASSERT_NO_MSG(id < ARRAY_SIZE(stream_nr)); in dma_stm32_id_to_stream()
35 return stream_nr[id]; in dma_stm32_id_to_stream()
58 void dma_stm32_clear_ht(DMA_TypeDef *DMAx, uint32_t id) in dma_stm32_clear_ht() argument
71 __ASSERT_NO_MSG(id < ARRAY_SIZE(func)); in dma_stm32_clear_ht()
73 func[id](DMAx); in dma_stm32_clear_ht()
76 void dma_stm32_clear_tc(DMA_TypeDef *DMAx, uint32_t id) in dma_stm32_clear_tc() argument
89 __ASSERT_NO_MSG(id < ARRAY_SIZE(func)); in dma_stm32_clear_tc()
91 func[id](DMAx); in dma_stm32_clear_tc()
94 bool dma_stm32_is_ht_active(DMA_TypeDef *DMAx, uint32_t id) in dma_stm32_is_ht_active() argument
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| D | dma_stm32_v2.c | 18 uint32_t dma_stm32_id_to_stream(uint32_t id) in dma_stm32_id_to_stream() argument
39 __ASSERT_NO_MSG(id < ARRAY_SIZE(stream_nr)); in dma_stm32_id_to_stream()
41 return stream_nr[id]; in dma_stm32_id_to_stream()
44 void dma_stm32_clear_ht(DMA_TypeDef *DMAx, uint32_t id) in dma_stm32_clear_ht() argument
65 __ASSERT_NO_MSG(id < ARRAY_SIZE(func)); in dma_stm32_clear_ht()
67 func[id](DMAx); in dma_stm32_clear_ht()
70 void dma_stm32_clear_tc(DMA_TypeDef *DMAx, uint32_t id) in dma_stm32_clear_tc() argument
91 __ASSERT_NO_MSG(id < ARRAY_SIZE(func)); in dma_stm32_clear_tc()
93 func[id](DMAx); in dma_stm32_clear_tc()
96 bool dma_stm32_is_ht_active(DMA_TypeDef *DMAx, uint32_t id) in dma_stm32_is_ht_active() argument
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| D | dma_stm32u5.c | 46 static void dma_stm32_dump_stream_irq(const struct device *dev, uint32_t id) in dma_stm32_dump_stream_irq() argument
51 stm32_dma_dump_stream_irq(dma, id); in dma_stm32_dump_stream_irq()
54 static void dma_stm32_clear_stream_irq(const struct device *dev, uint32_t id) in dma_stm32_clear_stream_irq() argument
59 dma_stm32_clear_tc(dma, id); in dma_stm32_clear_stream_irq()
60 dma_stm32_clear_ht(dma, id); in dma_stm32_clear_stream_irq()
61 stm32_dma_clear_stream_irq(dma, id); in dma_stm32_clear_stream_irq()
65 uint32_t dma_stm32_id_to_stream(uint32_t id) in dma_stm32_id_to_stream() argument
86 __ASSERT_NO_MSG(id < ARRAY_SIZE(stream_nr)); in dma_stm32_id_to_stream()
88 return stream_nr[id]; in dma_stm32_id_to_stream()
91 bool dma_stm32_is_tc_active(DMA_TypeDef *DMAx, uint32_t id) in dma_stm32_is_tc_active() argument
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| D | dma_stm32.h | 49 uint32_t dma_stm32_id_to_stream(uint32_t id);
51 uint32_t dma_stm32_slot_to_channel(uint32_t id);
61 bool dma_stm32_is_tc_active(DMA_TypeDef *DMAx, uint32_t id);
62 void dma_stm32_clear_tc(DMA_TypeDef *DMAx, uint32_t id);
63 bool dma_stm32_is_ht_active(DMA_TypeDef *DMAx, uint32_t id);
64 void dma_stm32_clear_ht(DMA_TypeDef *DMAx, uint32_t id);
65 bool dma_stm32_is_te_active(DMA_TypeDef *DMAx, uint32_t id);
66 void dma_stm32_clear_te(DMA_TypeDef *DMAx, uint32_t id);
69 bool dma_stm32_is_dme_active(DMA_TypeDef *DMAx, uint32_t id);
70 void dma_stm32_clear_dme(DMA_TypeDef *DMAx, uint32_t id);
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| D | dma_stm32_bdma.c | 38 uint32_t bdma_stm32_id_to_channel(uint32_t id) in bdma_stm32_id_to_channel() argument
51 __ASSERT_NO_MSG(id < ARRAY_SIZE(channel_nr)); in bdma_stm32_id_to_channel()
53 return channel_nr[id]; in bdma_stm32_id_to_channel()
76 void bdma_stm32_clear_ht(BDMA_TypeDef *DMAx, uint32_t id) in bdma_stm32_clear_ht() argument
89 __ASSERT_NO_MSG(id < ARRAY_SIZE(func)); in bdma_stm32_clear_ht()
91 func[id](DMAx); in bdma_stm32_clear_ht()
94 void bdma_stm32_clear_tc(BDMA_TypeDef *DMAx, uint32_t id) in bdma_stm32_clear_tc() argument
107 __ASSERT_NO_MSG(id < ARRAY_SIZE(func)); in bdma_stm32_clear_tc()
109 func[id](DMAx); in bdma_stm32_clear_tc()
112 bool bdma_stm32_is_ht_active(BDMA_TypeDef *DMAx, uint32_t id) in bdma_stm32_is_ht_active() argument
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| D | dma_stm32_bdma.h | 49 uint32_t bdma_stm32_id_to_channel(uint32_t id);
51 uint32_t bdma_stm32_slot_to_channel(uint32_t id);
57 bool bdma_stm32_is_gi_active(BDMA_TypeDef *DMAx, uint32_t id);
58 void bdma_stm32_clear_gi(BDMA_TypeDef *DMAx, uint32_t id);
60 void bdma_stm32_clear_tc(BDMA_TypeDef *DMAx, uint32_t id);
61 void bdma_stm32_clear_ht(BDMA_TypeDef *DMAx, uint32_t id);
62 bool bdma_stm32_is_te_active(BDMA_TypeDef *DMAx, uint32_t id);
63 void bdma_stm32_clear_te(BDMA_TypeDef *DMAx, uint32_t id);
65 bool stm32_bdma_is_irq_active(BDMA_TypeDef *dma, uint32_t id);
66 bool stm32_bdma_is_ht_irq_active(BDMA_TypeDef *ma, uint32_t id);
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| /Zephyr-Core-3.7.0/soc/atmel/sam/common/ |
| D | soc_pmc.c | 19 void soc_pmc_peripheral_enable(uint32_t id) in soc_pmc_peripheral_enable() argument
21 __ASSERT(id < ID_PERIPH_COUNT, "Invalid peripheral id"); in soc_pmc_peripheral_enable()
23 if (id < 32) { in soc_pmc_peripheral_enable()
24 PMC->PMC_PCER0 = BIT(id); in soc_pmc_peripheral_enable()
26 } else if (id < 64) { in soc_pmc_peripheral_enable()
27 PMC->PMC_PCER1 = BIT(id & 0x1F); in soc_pmc_peripheral_enable()
36 void soc_pmc_peripheral_disable(uint32_t id) in soc_pmc_peripheral_disable() argument
38 __ASSERT(id < ID_PERIPH_COUNT, "Invalid peripheral id"); in soc_pmc_peripheral_disable()
40 if (id < 32) { in soc_pmc_peripheral_disable()
41 PMC->PMC_PCDR0 = BIT(id); in soc_pmc_peripheral_disable()
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| /Zephyr-Core-3.7.0/drivers/reset/ |
| D | reset_nxp_rstctl.c | 15 #define NXP_RSTCTL_OFFSET(id) ((id >> 16) * sizeof(uint32_t)) argument
16 #define NXP_RSTCTL_BIT(id) (BIT(id & 0xFFFF)) argument
17 #define NXP_RSTCTL_CTL(id) (NXP_RSTCTL_OFFSET(id) + 0x10) argument
18 #define NXP_RSTCTL_SET(id) (NXP_RSTCTL_OFFSET(id) + 0x40) argument
19 #define NXP_RSTCTL_CLR(id) (NXP_RSTCTL_OFFSET(id) + 0x70) argument
21 static int reset_nxp_rstctl_status(const struct device *dev, uint32_t id, uint8_t *status) in reset_nxp_rstctl_status() argument
24 volatile const uint32_t *ctl_reg = base+(NXP_RSTCTL_CTL(id)/sizeof(uint32_t)); in reset_nxp_rstctl_status()
27 *status = (uint8_t)FIELD_GET(NXP_RSTCTL_BIT(id), val); in reset_nxp_rstctl_status()
32 static int reset_nxp_rstctl_line_assert(const struct device *dev, uint32_t id) in reset_nxp_rstctl_line_assert() argument
35 volatile uint32_t *set_reg = (uint32_t *)base+(NXP_RSTCTL_SET(id)/sizeof(uint32_t)); in reset_nxp_rstctl_line_assert()
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| D | reset_stm32.c | 14 #define STM32_RESET_CLR_OFFSET(id) (((id) >> 17U) & 0xFFFU) argument
15 #define STM32_RESET_SET_OFFSET(id) (((id) >> 5U) & 0xFFFU) argument
16 #define STM32_RESET_REG_BIT(id) ((id)&0x1FU) argument
22 static int reset_stm32_status(const struct device *dev, uint32_t id, in reset_stm32_status() argument
27 *status = !!sys_test_bit(config->base + STM32_RESET_SET_OFFSET(id), in reset_stm32_status()
28 STM32_RESET_REG_BIT(id)); in reset_stm32_status()
33 static int reset_stm32_line_assert(const struct device *dev, uint32_t id) in reset_stm32_line_assert() argument
37 sys_set_bit(config->base + STM32_RESET_SET_OFFSET(id), in reset_stm32_line_assert()
38 STM32_RESET_REG_BIT(id)); in reset_stm32_line_assert()
43 static int reset_stm32_line_deassert(const struct device *dev, uint32_t id) in reset_stm32_line_deassert() argument
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| D | reset_gd32.c | 14 /** RCU offset (from id field) */
15 #define GD32_RESET_ID_OFFSET(id) (((id) >> 6U) & 0xFFU) argument
16 /** RCU configuration bit (from id field) */
17 #define GD32_RESET_ID_BIT(id) ((id) & 0x1FU) argument
23 static int reset_gd32_status(const struct device *dev, uint32_t id, in reset_gd32_status() argument
28 *status = !!sys_test_bit(config->base + GD32_RESET_ID_OFFSET(id), in reset_gd32_status()
29 GD32_RESET_ID_BIT(id)); in reset_gd32_status()
34 static int reset_gd32_line_assert(const struct device *dev, uint32_t id) in reset_gd32_line_assert() argument
38 sys_set_bit(config->base + GD32_RESET_ID_OFFSET(id), in reset_gd32_line_assert()
39 GD32_RESET_ID_BIT(id)); in reset_gd32_line_assert()
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| D | reset_lpc_syscon.c | 15 #define LPC_RESET_OFFSET(id) (id >> 16) argument
16 #define LPC_RESET_BIT(id) (BIT(id & 0xFFFF)) argument
18 static int reset_nxp_syscon_status(const struct device *dev, uint32_t id, uint8_t *status) in reset_nxp_syscon_status() argument
20 const volatile uint32_t *ctrl_reg = ((uint32_t *)dev->config)+(LPC_RESET_OFFSET(id)); in reset_nxp_syscon_status()
21 *status = (uint8_t)FIELD_GET((uint32_t)LPC_RESET_BIT(id), *ctrl_reg); in reset_nxp_syscon_status()
26 static int reset_nxp_syscon_line_assert(const struct device *dev, uint32_t id) in reset_nxp_syscon_line_assert() argument
28 SYSCON->PRESETCTRLSET[LPC_RESET_OFFSET(id)] = FIELD_PREP(LPC_RESET_BIT(id), 0b1); in reset_nxp_syscon_line_assert()
33 static int reset_nxp_syscon_line_deassert(const struct device *dev, uint32_t id) in reset_nxp_syscon_line_deassert() argument
35 SYSCON->PRESETCTRLCLR[LPC_RESET_OFFSET(id)] = FIELD_PREP(LPC_RESET_BIT(id), 0b1); in reset_nxp_syscon_line_deassert()
40 static int reset_nxp_syscon_line_toggle(const struct device *dev, uint32_t id) in reset_nxp_syscon_line_toggle() argument
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| D | reset_numaker.c | 16 #define NUMAKER_RESET_IP_OFFSET(id) (NUMAKER_RESET_IPRST0_OFFSET + (((id) >> 24UL) & 0xffUL)) argument
18 #define NUMAKER_RESET_IP_BIT(id) (id & 0x00ffffffUL) argument
24 static int reset_numaker_status(const struct device *dev, uint32_t id, uint8_t *status) in reset_numaker_status() argument
28 *status = !!sys_test_bit(config->base + NUMAKER_RESET_IP_OFFSET(id), in reset_numaker_status()
29 NUMAKER_RESET_IP_BIT(id)); in reset_numaker_status()
34 static int reset_numaker_line_assert(const struct device *dev, uint32_t id) in reset_numaker_line_assert() argument
39 sys_set_bit(config->base + NUMAKER_RESET_IP_OFFSET(id), NUMAKER_RESET_IP_BIT(id)); in reset_numaker_line_assert()
44 static int reset_numaker_line_deassert(const struct device *dev, uint32_t id) in reset_numaker_line_deassert() argument
49 sys_clear_bit(config->base + NUMAKER_RESET_IP_OFFSET(id), NUMAKER_RESET_IP_BIT(id)); in reset_numaker_line_deassert()
54 static int reset_numaker_line_toggle(const struct device *dev, uint32_t id) in reset_numaker_line_toggle() argument
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| /Zephyr-Core-3.7.0/samples/subsys/sip_svc/ |
| D | README.rst | 39 Got response of transaction id 0x00 and voltage is 0.846878v
40 Got response of transaction id 0x01 and voltage is 0.858170v
41 Got response of transaction id 0x02 and voltage is 0.860168v
42 Got response of transaction id 0x03 and voltage is 0.846832v
43 Got response of transaction id 0x04 and voltage is 0.858337v
44 Got response of transaction id 0x05 and voltage is 0.871704v
45 Got response of transaction id 0x06 and voltage is 0.859421v
46 Got response of transaction id 0x07 and voltage is 0.857254v
47 Got response of transaction id 0x08 and voltage is 0.858429v
48 Got response of transaction id 0x09 and voltage is 0.859879v
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| /Zephyr-Core-3.7.0/subsys/sip_svc/ |
| D | sip_svc_id_mgr.c | 6 * Arm SiP services service ID manager and ID mapping table force
15 * Create a id key pool using size variable 0..size-1, where we can
16 * track the allocated id.
28 /* Allocate memory for ID pool */ in sip_svc_id_mgr_create()
53 /* Initialize ID */ in sip_svc_id_mgr_create()
58 /* ID pool is full during initialization */ in sip_svc_id_mgr_create()
62 /* Initialize ID in use flags */ in sip_svc_id_mgr_create()
70 /* Delete a created id pool*/
80 /* Retrieve an id from the id pool*/
83 uint32_t id; in sip_svc_id_mgr_alloc() local
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| /Zephyr-Core-3.7.0/subsys/net/lib/lwm2m/ |
| D | lwm2m_obj_access_control.h | 12 * @brief Main access control logic. Checks if the server with instance id @p server_obj_inst are
13 * allowed to do @p operation on the object instance of object id @p obj_id
14 * and object instance id @p obj_inst_id. If access control is enabled, this should
17 * @param obj_id object id of the object instance having its rights checked.
18 * @param obj_inst_id object instance id of the object instance having its rights checked.
19 * @param server_obj_inst object instance id of the server attempting to do the operation.
34 * @param obj_id object id of the object instance getting an access control.
35 * @param obj_inst_id object instance id of the object instance getting access control.
36 * @param server_obj_inst_id object instance id of the server creating the object instance.
42 * have access to create object instances of object id @p obj_id.
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| /Zephyr-Core-3.7.0/boards/native/doc/ |
| D | layering_natsim.svg | 10 id="svg152"
18 id="defs156" /><sodipodi:namedview
19 id="namedview154"
55 id="style2">
70 id="shape1-1"
75 id="title6">Sheet.1</title>
77 id="desc8">CPU/SOC</desc>
92 id="rect10" />
98 id="text12"><v:paragraph
100 id="shape2-4"
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| /Zephyr-Core-3.7.0/tests/drivers/can/api/src/ |
| D | common.c | 26 * @brief Standard (11-bit) CAN ID frame 1.
30 .id = TEST_CAN_STD_ID_1,
36 * @brief Standard (11-bit) CAN ID frame 2.
40 .id = TEST_CAN_STD_ID_2,
46 * @brief Extended (29-bit) CAN ID frame 1.
50 .id = TEST_CAN_EXT_ID_1,
56 * @brief Extended (29-bit) CAN ID frame 1.
60 .id = TEST_CAN_EXT_ID_2,
66 * @brief Standard (11-bit) CAN ID RTR frame 1.
70 .id = TEST_CAN_STD_ID_1,
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| /Zephyr-Core-3.7.0/tests/bluetooth/host/id/bt_id_delete/src/ |
| D | main.c | 18 #include <host/id.h>
36 * Test deleting an ID, but not the last one
39 * - ID value used is neither corresponds to default index nor the last index
42 * - bt_dev.id_addr[] at index equals to the ID value used is cleared
43 * - bt_dev.irk[] at index equals to the ID value used is cleared (if privacy is enabled)
49 uint8_t id; in ZTEST() local
56 id = 1; in ZTEST()
65 err = bt_id_delete(id); in ZTEST()
71 zassert_true(bt_dev.id_count == id_count, "Incorrect ID count %d was set", bt_dev.id_count); in ZTEST()
73 zassert_mem_equal(&bt_dev.id_addr[id], BT_ADDR_LE_ANY, sizeof(bt_addr_le_t), in ZTEST()
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| /Zephyr-Core-3.7.0/subsys/net/l2/ethernet/lldp/ |
| D | Kconfig | 52 # CHASSIS ID TLV CONFIG
55 int "Chassis ID TLV subtype"
59 Chassis ID subtype options are defined below.
74 hex "Chassis ID MAC Address Byte 0"
81 hex "Chassis ID MAC Address Byte 1"
88 hex "Chassis ID MAC Address Byte 2"
95 hex "Chassis ID MAC Address Byte 3"
102 hex "Chassis ID MAC Address Byte 4"
109 hex "Chassis ID MAC Address Byte 5"
117 string "Chassis ID value"
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