Searched full:i0 (Results 1 – 10 of 10) sorted by relevance
| /Zephyr-latest/arch/sparc/core/ |
| D | sw_trap_set_pil.S | 23 * - %i0: New processor interrupt level
26 * - %i0: Old processor interrupt level
30 sll %i0, PSR_PIL_BIT, %i0
32 or %l5, %i0, %l5
40 srl %l3, PSR_PIL_BIT, %i0
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| D | switch.S | 39 std %i0, [%o1 + _thread_offset_to_i0]
77 std %i0, [%sp + 0x20]
127 ldd [%o0 + _thread_offset_to_i0], %i0
153 mov %i0, %o0
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| D | window_trap.S | 33 std %i0, [%sp + 0x20]
69 ldd [%sp + 0x20], %i0
119 std %i0, [%sp + 0x20]
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| D | fault_trap.S | 63 std %i0, [%sp + 0x20]
84 std %i0, [%sp + 96 + __struct_arch_esf_out_OFFSET + 0x00]
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| D | thread.c | 40 thread->callee_saved.i0 = (uint32_t) entry; in arch_new_thread()
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| D | interrupt_trap.S | 69 std %i0, [%sp + 0x20]
315 ldd [%g1 + 0x20], %i0
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| /Zephyr-latest/arch/sparc/core/offsets/ |
| D | offsets.c | 27 GEN_OFFSET_SYM(_callee_saved_t, i0);
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| /Zephyr-latest/include/zephyr/arch/sparc/ |
| D | thread.h | 52 uint32_t i0; member
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| /Zephyr-latest/dts/bindings/sensor/ |
| D | nxp,s32-qdec.yaml | 8 The following example uses TRGMUX IN2 and IN3 to connect to LCU1 LC0 I0 and I1.
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| /Zephyr-latest/scripts/build/ |
| D | check_init_priorities_test.py | 218 return "i0"
233 "PRE_KERNEL_2": ["a: i0(__device_dts_ord_11)", "b: i1(__device_dts_ord_22)"],
239 11: (check_init_priorities.Priority("PRE_KERNEL_2", 0), "i0"),
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