1# Copyright (c) 2023, STMicroelectronics
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  STM32 Reset and Clock controller node.
6  This node is in charge of system clock ('SYSCLK') source selection and controlling
7  clocks for AHB (Advanced High Performance) and APB (Advanced Peripheral) bus domains.
8
9  Configuring STM32 Reset and Clock controller node:
10
11  System clock source should be selected amongst the clock nodes available in "clocks"
12  node (typically 'clk_hse, clk_hsi', 'pll').
13  Core clock frequency should also be defined, using "clock-frequency" property.
14  Note:
15          Core clock frequency  = SYSCLK / AHB prescaler
16  Last, peripheral bus clocks (typically PCLK1, PCLK2, PCLK7) should be configured using
17  matching prescaler properties.
18  Here is an example of correctly configured rcc node:
19  &rcc {
20           clocks = <&pll>;                   /* Select pll as SYSCLK source */
21           ahb-prescaler = <2>;
22           clock-frequency = <DT_FREQ_M(40)>; /* = SYSCLK / AHB prescaler */
23           apb1-presacler = <1>;
24           apb2-presacler = <1>;
25           apb7-presacler = <7>;
26  }
27
28  Specifying a gated clock:
29
30  To specify a gated clock, a peripheral should define a "clocks" property encoded
31  in the following way:
32  ... {
33           ...
34           clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
35           ...
36  }
37  After the phandle referring to rcc node, the first index specifies the registers of
38  the bus controlling the peripheral and the second index specifies the bit used to
39  control the peripheral clock in that bus register.
40
41  Specifying an alternate clock source:
42
43  Specifying an alternate source clock could be done by adding a clock specifier to the
44  clock property:
45  ... {
46           ...
47           clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>,
48                        <&rcc STM32_SRC_HSI I2C1_SEL(2)>;
49           ...
50  }
51  In this example I2C1 device is assigned HSI as clock source.
52  It is device driver's responsibility to querry and use clock source information in
53  accordance with clock_control API specifications.
54
55compatible: "st,stm32wba-rcc"
56
57include: [clock-controller.yaml, base.yaml]
58
59properties:
60  reg:
61    required: true
62
63  "#clock-cells":
64    const: 2
65
66  clock-frequency:
67    required: true
68    type: int
69    description: |
70      default frequency in Hz for clock output (HCLK1)
71
72  ahb-prescaler:
73    type: int
74    required: true
75    enum:
76      - 1
77      - 2
78      - 4
79      - 8
80      - 16
81    description: |
82        Common AHB1, AHB2, AHB4 prescaler. Defines actual core clock frequency
83        (HCLK) based on system frequency input. AKA HPRE.
84        The HCLK clocks CPU, AHB1, AHB2, memories and DMA.
85
86  ahb5-prescaler:
87    type: int
88    enum:
89      - 1
90      - 2
91      - 3
92      - 4
93      - 6
94    description: |
95        AHB5 prescaler. Defines actual core clock frequency (HCLK5) based on
96        system frequency input. It is used to limit HCLK5 below 32MHz.
97        Only required when SysClock source is PLL1.
98        AKA HPRE5.
99
100  apb1-prescaler:
101    type: int
102    required: true
103    enum:
104      - 1
105      - 2
106      - 4
107      - 8
108      - 16
109
110  apb2-prescaler:
111    type: int
112    required: true
113    enum:
114      - 1
115      - 2
116      - 4
117      - 8
118      - 16
119
120  apb7-prescaler:
121    type: int
122    required: true
123    enum:
124      - 1
125      - 2
126      - 4
127      - 8
128      - 16
129
130  ahb5-div:
131    type: boolean
132    description: |
133      AHB5 divider. Applies only when SysClock source is HSI16 or HSE32.
134      When enabled, AHB5 clock is SysClock / 2.
135      When disabled, SysClock is not divided.
136
137clock-cells:
138  - bus
139  - bits
140