1# Copyright (c) 2021, Linaro ltd
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  STM32WB Reset and Clock controller node.
6  For more description confere st,stm32-rcc.yaml
7
8compatible: "st,stm32wb-rcc"
9
10include:
11  - name: st,stm32-rcc.yaml
12    property-blocklist:
13      - ahb-prescaler
14
15properties:
16  cpu1-prescaler:
17    type: int
18    required: true
19    enum:
20      - 1
21      - 2
22      - 3
23      - 4
24      - 5
25      - 6
26      - 8
27      - 10
28      - 16
29      - 32
30      - 64
31      - 128
32      - 256
33      - 512
34    description: |
35        CPU1 prescaler. Sets a HCLK1 frequency (Core frequency)
36        lower than SYSCLK frequency.
37        The HCLK1 clocks CPU1, AHB1, AHB2, AHB3 and SRAM1.
38
39  cpu2-prescaler:
40    type: int
41    required: true
42    enum:
43      - 1
44      - 2
45      - 4
46      - 8
47      - 16
48      - 32
49      - 64
50      - 128
51      - 256
52      - 512
53    description: |
54        CPU2 prescaler. Sets HCLK2 frequency which clocks CPU2.
55        (A.K.A C2HPRE)
56
57  ahb4-prescaler:
58    type: int
59    required: true
60    enum:
61      - 1
62      - 2
63      - 4
64      - 8
65      - 16
66      - 32
67      - 64
68      - 128
69      - 256
70      - 512
71    description: |
72        HCLK4 shared prescaler (AHB4, Flash memory and SRAM2).
73        (A.K.A SHDHPRE)
74
75clock-cells:
76  - bus
77  - bits
78