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/Zephyr-Core-2.7.6/soc/arm/st_stm32/common/
Dstm32cube_hal.c2 * Copyright (c) 2018, I-SENSE group of ICCS
4 * SPDX-License-Identifier: Apache-2.0
9 * @brief Zephyr's implementation for STM32Cube HAL core initialization
11 * STM32Cube HAL in order to be overwritten in case of other
19 * Cube HAL expects a 1ms tick which matches with k_uptime_get_32.
21 * @return HAL status
29 * @brief This function provides minimum delay (in milliseconds) based
41 * @brief Generates an assert on STM32Cube HAL/LL assert trigger.
/Zephyr-Core-2.7.6/drivers/crypto/
DKconfig.nrf_ecb4 # SPDX-License-Identifier: Apache-2.0
7 DT_COMPAT_NORDIC_NRF_ECB := nordic,nrf-ecb
13 # (see subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/ecb.c),
17 Enable nRF HAL-based AES ECB encryption driver
DKconfig.stm323 # Copyright (c) 2020 Markus Fuchs <markus.fuchs@de.sauter-bc.com>
4 # SPDX-License-Identifier: Apache-2.0
6 DT_COMPAT_ST_STM32_AES := st,stm32-aes
7 DT_COMPAT_ST_STM32_CRYP := st,stm32-cryp
16 Enable STM32 HAL-based Cryptographic Accelerator driver.
/Zephyr-Core-2.7.6/
Dwest.yml3 # The per-installation west configuration file, .west/config, sets the
22 - name: upstream
23 url-base: https://github.com/zephyrproject-rtos
26 # Please add items below based on alphabetical order
28 - name: canopennode
31 - name: civetweb
34 - name: cmsis
36 path: modules/hal/cmsis
38 - hal
39 - name: edtt
[all …]
/Zephyr-Core-2.7.6/drivers/ethernet/
DKconfig.stm32_hal1 # STM32 HAL Ethernet driver configuration options
5 # SPDX-License-Identifier: Apache-2.0
7 DT_COMPAT_ST_STM32_ETHERNET := st,stm32-ethernet
10 bool "STM32 HAL Ethernet driver"
15 Enable STM32 HAL based Ethernet driver. It is available for
89 PHY's carrier status is re-evaluated.
/Zephyr-Core-2.7.6/dts/bindings/i2c/
Dnordic,nrf-twis.yaml2 # SPDX-License-Identifier: Apache-2.0
8 these devices. See this issue for more details and a HAL-based
11 https://github.com/zephyrproject-rtos/zephyr/issues/21445
16 TWIS by setting the node's "compatible" to "nordic,nrf-twis"
19 /* This is for TWIS0 -- change to "i2c1" for TWIS1, etc. */
21 compatible = "nordic,nrf-twis";
28 compatible: "nordic,nrf-twis"
30 include: nordic,nrf-twi-common.yaml
33 address-0:
38 address-1:
Datmel,sam-i2c-twim.yaml2 # SPDX-License-Identifier: Apache-2.0
7 The Atmel Two-wire Master Interface (TWIM) interconnects components on a
8 unique two-wire bus, made up of one clock line and one data line with speeds
9 of up to 3.4 Mbit/s, based on a byte-oriented transfer format. The TWIM is
20 std-clk-slew-lim = <0>;
21 std-clk-strength-low = "0.5";
22 std-data-slew-lim = <0>;
23 std-data-strength-low = "0.5";
25 hs-clk-slew-lim = <0>;
26 hs-clk-strength-high = "0.5";
[all …]
/Zephyr-Core-2.7.6/subsys/bluetooth/controller/ll_sw/
Dull_chan.c4 * SPDX-License-Identifier: Apache-2.0
18 #include "hal/ccm.h"
36 * periodic, and isochronous physical channels based on its local information.
Dlll_common.c4 * SPDX-License-Identifier: Apache-2.0
19 #include "hal/debug.h"
32 * @param event_prio Priority of event [-128..127]
38 * -EINPROGRESS: Event already in progress and prepare was queued
46 struct lll_hdr *hdr = prepare_param->param; in lll_prepare()
48 /* Establish priority based on: in lll_prepare()
50 * 2. Force flag => priority = -127 in lll_prepare()
51 * 3. Score (events terminated- and too late) in lll_prepare()
52 * 4. Latency (skipped- and programmed latency) in lll_prepare()
53 * 5. Critical priority is immutable (-128) in lll_prepare()
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/Zephyr-Core-2.7.6/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/
Dradio_nrf5_dppi.h2 * Copyright (c) 2018 - 2020 Nordic Semiconductor ASA
5 * SPDX-License-Identifier: Apache-2.0
10 #include <hal/nrf_dppi.h>
11 #include <hal/nrf_timer.h>
12 #include <hal/nrf_radio.h>
13 #include <hal/nrf_rtc.h>
14 #include <hal/nrf_ccm.h>
15 #include <hal/nrf_aar.h>
16 #include <hal/nrf_gpiote.h>
277 /* DPPI setup used for SW-based auto-switching during TIFS. */
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/Zephyr-Core-2.7.6/cmake/compiler/xcc/
Dtarget.cmake1 # SPDX-License-Identifier: Apache-2.0
5 # Configures CMake for using GCC, this script is re-used by several
6 # GCC-based toolchains
29 set(NOSYSDEF_CFLAG -undef)
32 foreach(file_name include/stddef.h include-fixed/limits.h)
34 COMMAND ${CMAKE_C_COMPILER} --print-file-name=${file_name}
45 hal
56 list(APPEND isystem_include_flags -isystem "\"${isystem_include_dir}\"")
65 # toolchain-specific flags at generation time.
66 …st(APPEND CMAKE_REQUIRED_FLAGS -nostartfiles -nostdlib ${isystem_include_flags} -Wl,--unresolved-s…
/Zephyr-Core-2.7.6/dts/bindings/ethernet/
Datmel,gmac-common.yaml2 # Copyright (c) 2020-2021 Gerson Fernando Budke <nandojve@gmail.com>
3 # SPDX-License-Identifier: Apache-2.0
11 num-queues:
17 max-frame-size:
23 means that normally gmac will reject any frame above max-frame-size
33 max-speed:
41 phy-connection-type:
44 - "rmii"
45 - "mii"
50 represents Reduced Media-Independent Interface (RMII) mode.
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/Zephyr-Core-2.7.6/samples/boards/nrf/system_off/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
13 #include <hal/nrf_gpio.h>
65 printk("Busy-wait %u s\n", BUSY_WAIT_S); in main()
68 printk("Busy-wait %u s with UART off\n", BUSY_WAIT_S); in main()
89 /* Above we disabled entry to deep sleep based on duration of in main()
97 /* spin to avoid fall-off behavior */ in main()
/Zephyr-Core-2.7.6/include/toolchain/
Dxcc.h4 * SPDX-License-Identifier: Apache-2.0
110 /* XCC (GCC-based compiler) doesn't support __COUNTER__
131 * HAL defines similar ones. Thus we include it and define the missing macros
/Zephyr-Core-2.7.6/soc/arm/atmel_sam/same70/
Dsoc.c3 * SPDX-License-Identifier: Apache-2.0
9 * This file provides routines to initialize and support board-level hardware
64 SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_XTALSEL; in clock_init()
67 while (!(SUPC->SUPC_SR & SUPC_SR_OSCSEL)) { in clock_init()
78 if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL_Msk)) { in clock_init()
80 PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD in clock_init()
92 while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) { in clock_init()
97 PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD in clock_init()
104 while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)) { in clock_init()
110 PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD in clock_init()
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/Zephyr-Core-2.7.6/soc/arm/atmel_sam/samv71/
Dsoc.c4 * SPDX-License-Identifier: Apache-2.0
10 * This file provides routines to initialize and support board-level hardware
65 SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_XTALSEL; in clock_init()
68 while (!(SUPC->SUPC_SR & SUPC_SR_OSCSEL)) { in clock_init()
79 if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL_Msk)) { in clock_init()
81 PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD in clock_init()
93 while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) { in clock_init()
98 PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD in clock_init()
105 while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)) { in clock_init()
111 PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD in clock_init()
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/Zephyr-Core-2.7.6/doc/releases/
Drelease-notes-1.11.rst12 * Thread-level memory protection on x86, ARC and Arm, userspace and memory
15 * Initial Armv8-M architecture support.
20 * Firmware over-the-air (FOTA) updates over BLE using MCUmgr.
32 * SMP-aware scheduler
47 * Armv8-M initial architecture support, including the following cores:
49 * Arm Cortex-M23
50 * Arm Cortex-M33
74 * Refactored dts.fixup so common SoC-related fixes are in arch/<*>/soc
75 and board dts.fixup is only used for board-specific items.
82 * Added I2C master, QSPI flash, and GPIO drivers for nios-II
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Drelease-notes-2.0.rst12 * The kernel now supports both 32- and 64-bit architectures.
17 * We added support for :ref:`Point-to-Point Protocol (PPP) <ppp>`. PPP is a
20 * We added support for UpdateHub, an end-to-end solution for large scale
21 over-the-air device updates.
22 * We added support for ARM Cortex-R Architecture (Experimental).
32 * Fixes CVE-2019-9506: The Bluetooth BR/EDR specification up to and
35 negotiation. This allows practical brute-force attacks (aka "KNOB")
42 * New kernel API for per-thread disabling of Floating Point Services for
43 ARC, ARM Cortex-M, and x86 architectures.
45 * Additional support for compatibility with 64-bit architectures.
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Drelease-notes-2.1.rst13 * Expanded support for ARMv6-M architecture.
50 hardware-based stack overflow detection) in ARMv6-M architecture
51 * Added QEMU support for ARMv6-M architecture
52 * Extended test coverage for ARM-specific kernel features in ARMv6-M
54 * Enhanced runtime MPU programming in ARMv8-M architecture, making
55 the full partitioning of kernel SRAM memory a user-configurable
57 * Added CMSIS support for Cortex-R architectures.
59 * Added missing Cortex-R CPU device tree bindings.
60 * Fixed incorrect Cortex-R device tree specification.
68 * RISC-V:
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Drelease-notes-1.13.rst16 * Support for IEEE 802.1AS-2011 generalized Precision Time Protocol (gPTP)
23 * Basic support for Arm TrustZone in Armv8-M
42 * arch: arm: implement ARMv8-M MPU driver
44 * arch: arm: macro API for defining non-secure entry functions
48 * arch: ARM: Change the march used by cortex-m0 and cortex-m0plus
50 * arch: arm: basic Arm TrustZone-M functionality for Cortex-M23 and Cortex-M33
51 * arch: arm: built-in stack protection using Armv8-M SPLIM registers
52 * arch: arm: API for using TT intrinsics in Secure/Non-Secure Armv8-M firmware
63 * riscv32: riscv-privilege: Microsemi Mi-V support
99 * modem: Added Wistron WNC-M14A2A LTE-M Modem driver
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Drelease-notes-1.10.rst12 * Initial alpha-quality thread-level memory protection on x86, userspace and memory
27 * Initial alpha-quality thread-level memory protection on x86, userspace and memory
35 * Memory domain APIs for fine-tuning memory region permissions
38 * Add the following application-facing memory domain APIs:
40 * k_mem_domain_init() - to initialize a memory domain
41 * k_mem_domain_destroy() - to destroy a memory domain
42 * k_mem_domain_add_partition() - to add a partition into a domain
43 * k_mem_domain_remove_partition() - to remove a partition from a domain
44 * k_mem_domain_add_thread() - to add a thread into a domain
45 * k_mem_domain_remove_thread() - to remove a thread from a domain
[all …]
/Zephyr-Core-2.7.6/soc/riscv/openisa_rv32m1/
Dsoc.c4 * SPDX-License-Identifier: Apache-2.0
28 * Run-mode configuration for the fast internal reference clock (FIRC).
40 * FIRC-based system clock configuration.
66 EVENT_UNIT->SLPCTRL |= EVENT_SLPCTRL_SYSRSTREQST_MASK; in sys_arch_reboot()
75 EVENT_UNIT->INTPTEN |= BIT(rv32m1_level1_irq(irq)); in arch_irq_enable()
77 (void)(EVENT_UNIT->INTPTEN); in arch_irq_enable()
82 EVENT_UNIT->INTPTEN |= BIT(rv32m1_level1_irq(irq)); in arch_irq_enable()
83 (void)(EVENT_UNIT->INTPTEN); in arch_irq_enable()
93 EVENT_UNIT->INTPTEN &= ~BIT(rv32m1_level1_irq(irq)); in arch_irq_disable()
95 (void)(EVENT_UNIT->INTPTEN); in arch_irq_disable()
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/Zephyr-Core-2.7.6/boards/arm/stm32h735g_disco/doc/
Dindex.rst9 The STM32H735G-DK Discovery kit is a complete demonstration and development
10 platform for Arm® Cortex®-M7 core-based STM32H735IGK6U microcontroller, with
13 The STM32H735G-DK Discovery kit is used as a reference design for user
21 Octo-SPI Flash memory, RGB interface LCD with capacitive touch panel, and others).
25 STLINK-V3E is integrated into the board, as the embedded in-circuit debugger and
26 programmer for the STM32 MCU and USB Virtual COM port bridge. STM32H735G-DK board
28 software HAL library as well as various software examples.
34 :alt: STM32H735G-DISCO
36 More information about the board can be found at the `STM32H735G-DISCO website`_.
39 - `STM32H725/735 on www.st.com`_
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/Zephyr-Core-2.7.6/drivers/flash/
Dsoc_flash_nios2_qspi.c4 * SPDX-License-Identifier: Apache-2.0
8 * This driver is written based on the Altera's
9 * Nios-II QSPI Controller HAL driver.
29 * Remove the following macros once the Altera HAL
75 struct flash_nios2_qspi_config *flash_cfg = dev->data; in flash_nios2_qspi_erase()
76 alt_qspi_controller2_dev *qspi_dev = &flash_cfg->qspi_dev; in flash_nios2_qspi_erase()
83 k_sem_take(&flash_cfg->sem_lock, K_FOREVER); in flash_nios2_qspi_erase()
93 if (((offset + len) > qspi_dev->data_end) || in flash_nios2_qspi_erase()
95 (NIOS2_WRITE_BLOCK_SIZE - 1)))) { in flash_nios2_qspi_erase()
97 rc = -EINVAL; in flash_nios2_qspi_erase()
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/Zephyr-Core-2.7.6/boards/arm/nucleo_l011k4/doc/
Dindex.rst8 The STM32 Nucleo-32 development board with STM32L011K4 MCU, supports Arduino Nano V3 connectivity.
18 The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer.
20 The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together
35 - STM32 microcontroller in LQFP32 package
36 - Extension resource:
38 - Arduino* Nano V3 connectivity
40 - ARM* mbed*
41 - On-board ST-LINK/V2-1 debugger/programmer with SWD connector:
43 - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1
45 - Flexible board power supply:
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