Searched full:gpio5 (Results 1 – 25 of 50) sorted by relevance
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| /Zephyr-Core-3.5.0/dts/bindings/regulator/ |
| D | regulator-gpio.yaml | 15 enable-gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
17 gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>, <&gpio5 2 GPIO_ACTIVE_HIGH>;
72 enable-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
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| /Zephyr-Core-3.5.0/tests/drivers/gpio/gpio_basic_api/boards/ |
| D | udoo_neo_full_m4.overlay | 10 out-gpios = <&gpio5 14 0>; /* J4 pin 4 */
11 in-gpios = <&gpio5 15 0>; /* J4 pin 3 */
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| /Zephyr-Core-3.5.0/dts/bindings/sound/ |
| D | cirrus,cs47l63.yaml | 44 gpio5-gpios:
47 GPIO5 input with bus-keeper
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| /Zephyr-Core-3.5.0/soc/arm/nxp_kinetis/kwx/ |
| D | soc_kw2xd.c | 80 * depends on the state of GPIO5 during transceiver reset. The frequency
81 * will be 4 MHz if the GPIO5 pin is low, otherwise it will be 32.78689 kHz.
90 /* Set PORTC.0 as output - modem GPIO5 pin */ in set_modem_clock()
98 /* Clear modem GPIO5 pin */ in set_modem_clock()
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| /Zephyr-Core-3.5.0/boards/arm/xmc47_relax_kit/ |
| D | xmc47_relax_kit.dts | 30 gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
33 gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
163 &gpio5 {
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| /Zephyr-Core-3.5.0/dts/bindings/gpio/ |
| D | raspberrypi,pico-header.yaml | 17 5 GPIO5/I2C0_SCL GPIO28/ADC2 28
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| D | raspberrypi-40pins-header.yaml | 25 19 GPIO5 GND -
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| /Zephyr-Core-3.5.0/boards/arm/qemu_cortex_m3/ |
| D | qemu_cortex_m3.dts | 67 &gpio5 {
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| /Zephyr-Core-3.5.0/boards/arm/mimxrt595_evk/ |
| D | mimxrt595_evk_cm33.dts | 94 <16 0 &gpio5 0 0>, /* D10 */
95 <17 0 &gpio5 1 0>, /* D11 */
96 <18 0 &gpio5 2 0>, /* D12 */
97 <19 0 &gpio5 3 0>, /* D13 */
306 &gpio5 {
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| /Zephyr-Core-3.5.0/boards/arm/vmu_rt1170/ |
| D | vmu_rt1170.dtsi | 20 gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
25 gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
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| D | vmu_rt1170.dts | 117 enable-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
140 &gpio5 {
432 int-gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>;
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| /Zephyr-Core-3.5.0/dts/bindings/i2c/ |
| D | ti,tca954x-base.yaml | 20 reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
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| /Zephyr-Core-3.5.0/boards/arm/udoo_neo_full_m4/ |
| D | udoo_neo_full_m4.dts | 66 &gpio5 {
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| /Zephyr-Core-3.5.0/dts/arm/infineon/ |
| D | xmc4500_F100x1024.dtsi | 87 gpio5: gpio@48028500 { label
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| D | xmc4700_F144x2048.dtsi | 86 gpio5: gpio@48028500 { label
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| /Zephyr-Core-3.5.0/dts/arm/nxp/ |
| D | nxp_rt1015.dtsi | 129 &gpio5{
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| D | nxp_rt1020.dtsi | 158 &gpio5{
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| D | nxp_imx8m_m4.dtsi | 110 gpio5: gpio@30240000 { label
316 &gpio5{
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| D | nxp_imx8ml_m7.dtsi | 145 gpio5: gpio@30240000 { label
320 &gpio5{
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| D | nxp_rt1050.dtsi | 170 &gpio5{
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| D | nxp_rt1024.dtsi | 170 &gpio5{
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| /Zephyr-Core-3.5.0/dts/arm/ti/ |
| D | lm3s6965.dtsi | 119 gpio5: gpio@40025000 { label
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| /Zephyr-Core-3.5.0/dts/arm/renesas/rcar/gen3/ |
| D | rcar_gen3_cr7.dtsi | 44 gpio5: gpio@e6055000 { label
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| /Zephyr-Core-3.5.0/soc/arm/nxp_imx/mcimx6x_m4/ |
| D | soc.c | 66 #if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio5), okay) in SOC_RdcInit()
68 RDC_SetPdapAccess(RDC, rdcPdapGpio5, RDC_DT_VAL(gpio5), false, false); in SOC_RdcInit()
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| /Zephyr-Core-3.5.0/boards/arm/mimxrt1062_fmurt6/ |
| D | mimxrt1062_fmurt6.dts | 102 enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
155 &gpio5 {
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