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/Zephyr-Core-3.7.0/boards/adi/max32655fthr/
Dmax32655fthr_max32655_m4.dts86 <10 0 &gpio2 7 0>, /* TX */
87 <9 0 &gpio2 6 0>, /* RX */
91 <5 0 &gpio2 5 0>, /* AIN5 */
92 <4 0 &gpio2 4 0>, /* AIN4 */
93 <3 0 &gpio2 3 0>, /* AIN3 */
94 <2 0 &gpio2 2 0>, /* AIN2 */
95 <1 0 &gpio2 1 0>, /* AIN1 */
96 <0 0 &gpio2 0 0>; /* AIN0 */
121 &gpio2 {
/Zephyr-Core-3.7.0/boards/infineon/xmc47_relax_kit/
Darduino_r3_connector.dtsi18 <6 0 &gpio2 15 0>, /* D0 */
19 <7 0 &gpio2 14 0>, /* D1 */
23 <11 0 &gpio2 12 0>, /* D5 */
24 <12 0 &gpio2 11 0>, /* D6 */
45 &gpio2 {
/Zephyr-Core-3.7.0/boards/nxp/lpcxpresso11u68/
Dlpcxpresso11u68.dts50 gpios = <&gpio2 16 GPIO_ACTIVE_LOW>;
54 gpios = <&gpio2 17 GPIO_ACTIVE_LOW>;
58 gpios = <&gpio2 18 GPIO_ACTIVE_LOW>;
74 <6 0 &gpio2 11 0>, /* D0 */
75 <7 0 &gpio2 12 0>, /* D1 */
83 <15 0 &gpio2 3 0>, /* D9 */
127 &gpio2 {
/Zephyr-Core-3.7.0/dts/bindings/gpio/
Dxlnx,xps-gpio-1.00.a.yaml44 1 if controller has GPIO2 enabled, 0 otherwise
59 Default output value. If n-th bit is 1, GPIO2-n default value is 1.
61 xlnx,gpio2-width:
69 Default tristate register value. If n-th bit is 1, GPIO2-n is an input.
Dxlnx,xps-gpio-1.00.a-gpio2.yaml1 description: Xilinx AXI GPIO IP GPIO2 node
3 compatible: "xlnx,xps-gpio-1.00.a-gpio2"
/Zephyr-Core-3.7.0/boards/nxp/imx93_evk/
Dimx93_evk_mimx9352_a55.dts42 gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>;
46 gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>;
50 gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
59 gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
64 gpios = <&gpio2 24 GPIO_ACTIVE_LOW>;
162 &gpio2{
/Zephyr-Core-3.7.0/tests/drivers/gpio/gpio_basic_api/boards/
Dimx93_evk_mimx9352_a55.overlay10 out-gpios = <&gpio2 13 0>;
11 in-gpios = <&gpio2 14 0>;
Dmax32680evkit_max32680_m4.overlay10 out-gpios = <&gpio2 6 0>;
11 in-gpios = <&gpio2 7 0>;
Dmax32655evkit_max32655_m4.overlay10 out-gpios = <&gpio2 0 0>;
11 in-gpios = <&gpio2 1 0>;
Dmax32655fthr_max32655_m4.overlay10 out-gpios = <&gpio2 0 0>;
11 in-gpios = <&gpio2 1 0>;
Dmax32690evkit_max32690_m4.overlay10 out-gpios = <&gpio2 7 0>;
11 in-gpios = <&gpio2 8 0>;
/Zephyr-Core-3.7.0/boards/snps/em_starterkit/
Dboard.dtsi85 gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
91 gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
97 gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
103 gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
/Zephyr-Core-3.7.0/boards/nxp/vmu_rt1170/
Dvmu_rt1170_mimxrt1176_cm7.dts54 enable-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
63 enable-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
72 enable-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
102 enable-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>;
112 enable-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
139 &gpio2 {
248 cs-gpios =<&gpio2 11 GPIO_ACTIVE_LOW>;
271 int-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
284 cs-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>,
285 <&gpio2 18 GPIO_ACTIVE_LOW>;
[all …]
/Zephyr-Core-3.7.0/tests/drivers/uart/uart_async_api/boards/
Desp32c6_devkitc.overlay11 input-enable; /* Connect GPIO2 and GPIO3 externally for testing */
15 output-enable; /* Connect GPIO2 and GPIO3 externally for testing */
/Zephyr-Core-3.7.0/boards/microchip/mpfs_icicle/
Dmpfs_icicle.dts32 gpios = <&gpio2 16 GPIO_ACTIVE_LOW>;
40 gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
77 &gpio2 {
Dmpfs_icicle_smp.dts39 gpios = <&gpio2 16 GPIO_ACTIVE_LOW>;
47 gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
84 &gpio2 {
/Zephyr-Core-3.7.0/samples/boards/esp32/deep_sleep/
DREADME.rst21 uses GPIO2 and GPIO4 to trigger a wake up with any one of the two pins are
37 However, when ``EXT1`` is also enabled, GPIO2 and GPIO4 should be pulled-down
65 sample below is for GPIO2.
73 Enabling EXT1 wakeup on pins GPIO2, GPIO4
/Zephyr-Core-3.7.0/boards/nxp/mimxrt1015_evk/
Dmimxrt1015_evk.dts45 gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
63 <8 0 &gpio2 20 0>, /* D2 */
64 <9 0 &gpio2 26 0>, /* D3 */
66 <11 0 &gpio2 27 0>, /* D5 */
69 <14 0 &gpio2 21 0>, /* D8 */
70 <15 0 &gpio2 22 0>, /* D9 */
/Zephyr-Core-3.7.0/include/zephyr/devicetree/
Dspi.h37 * <&gpio2 20 GPIO_ACTIVE_LOW>;
62 * <&gpio2 20 GPIO_ACTIVE_LOW>;
89 * <&gpio2 20 GPIO_ACTIVE_LOW>;
126 * gpio2: gpio@... { ... };
131 * <&gpio2 20 GPIO_ACTIVE_LOW>;
145 * DT_SPI_DEV_CS_GPIOS_CTLR(DT_NODELABEL(b)) // DT_NODELABEL(gpio2)
164 * <&gpio2 20 GPIO_ACTIVE_LOW>;
/Zephyr-Core-3.7.0/boards/nordic/nrf54l15pdk/
Dnrf54l15pdk_nrf54l15_common_0_2_1.dtsi32 gpios = <&gpio2 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
36 gpios = <&gpio2 10 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
/Zephyr-Core-3.7.0/tests/drivers/spi/spi_loopback/socs/
Desp32c6.overlay11 output-enable; /* Connect GPIO2 and GPIO3 externally for testing */
15 input-enable; /* Connect GPIO2 and GPIO3 externally for testing */
/Zephyr-Core-3.7.0/samples/basic/blinky_pwm/
DREADME.rst57 - connect GPIO2 to an LED
59 - connect GPIO2 to an LED
61 - connect GPIO2 to an LED
/Zephyr-Core-3.7.0/dts/bindings/sound/
Dcirrus,cs47l63.yaml29 gpio2-gpios:
32 GPIO2 input with bus-keeper
/Zephyr-Core-3.7.0/samples/boards/esp32/deep_sleep/boards/
Desp32_devkitc_wroom_procpu.conf1 # Enables GPIO2 and GPIO4 as wakeup sources
Desp32s2_saola.conf1 # Enables GPIO2 and GPIO4 as wakeup sources

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