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/Zephyr-Core-3.5.0/dts/bindings/gpio/
Dxlnx,xps-gpio-1.00.a.yaml3 compatible: "xlnx,xps-gpio-1.00.a"
5 include: [gpio-controller.yaml, base.yaml]
7 bus: xlnx,xps-gpio-1.00.a
10 # https://github.com/Xilinx/device-tree-xlnx
16 xlnx,all-inputs:
21 xlnx,all-outputs:
26 xlnx,dout-default:
29 Default output value. If n-th bit is 1, GPIO-n default value is 1.
31 xlnx,gpio-width:
36 xlnx,tri-default:
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Datmel-xplained-pro-header.yaml2 # SPDX-License-Identifier: Apache-2.0
9 names EXTn where n ϵ [1…7], n is determined by which ID pin is connected
28 https://www.microchip.com/development-tools/xplained-boards
29 …http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-42091-Atmel-Xplained-Pro-Hardware-Developmen…
37 0 ADC(+) 3 4 ADC(-) 1
38 2 UART(RTS)/GPIO1 5 6 UART(CTS)/GPIO2 3
39 4 PWM(+) 7 8 PWM(-) 5
47 compatible: "atmel-xplained-pro-header"
49 include: [gpio-nexus.yaml, base.yaml]
Dgpio-controller.yaml2 # SPDX-License-Identifier: Apache-2.0
7 "gpio-controller":
11 "#gpio-cells":
19 This property indicates the number of in-use slots of available slots
28 gpio-reserved-ranges:
31 If not all the GPIOs at offsets 0...N-1 are usable for ngpios = <N>, then
36 For example, setting "gpio-reserved-ranges = <3 2>, <10 1>;" means that
38 gpio-line-names:
39 type: string-array
44 child-binding:
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/Zephyr-Core-3.5.0/include/zephyr/devicetree/
Dgpio.h10 * SPDX-License-Identifier: Apache-2.0
21 * @defgroup devicetree-gpio Devicetree GPIO API
28 * gpio phandle-array property at an index
34 * gpio2: gpio@... { };
36 * n: node {
38 * <&gpio2 30 GPIO_ACTIVE_HIGH>;
43 * DT_GPIO_CTLR_BY_IDX(DT_NODELABEL(n), gpios, 1) // DT_NODELABEL(gpio2)
46 * @param gpio_pha lowercase-and-underscores GPIO property with
47 * type "phandle-array"
59 * @param gpio_pha lowercase-and-underscores GPIO property with
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/Zephyr-Core-3.5.0/drivers/gpio/
Dgpio_xlnx_axi.c4 * SPDX-License-Identifier: Apache-2.0
67 const struct gpio_xlnx_axi_config *config = dev->config; in gpio_xlnx_axi_read_data()
69 return sys_read32(config->base + (config->channel * GPIO2_OFFSET) + GPIO_DATA_OFFSET); in gpio_xlnx_axi_read_data()
74 const struct gpio_xlnx_axi_config *config = dev->config; in gpio_xlnx_axi_write_data()
76 sys_write32(val, config->base + (config->channel * GPIO2_OFFSET) + GPIO_DATA_OFFSET); in gpio_xlnx_axi_write_data()
81 const struct gpio_xlnx_axi_config *config = dev->config; in gpio_xlnx_axi_write_tri()
83 sys_write32(val, config->base + (config->channel * GPIO2_OFFSET) + GPIO_TRI_OFFSET); in gpio_xlnx_axi_write_tri()
88 const struct gpio_xlnx_axi_config *config = dev->config; in gpio_xlnx_axi_pin_configure()
89 struct gpio_xlnx_axi_data *data = dev->data; in gpio_xlnx_axi_pin_configure()
92 if (!(BIT(pin) & config->common.port_pin_mask)) { in gpio_xlnx_axi_pin_configure()
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Dgpio_lpc11u6x.c5 * SPDX-License-Identifier: Apache-2.0
78 * This structure is included by all the per-port private configuration.
108 const struct gpio_lpc11u6x_config *config = port->config; in gpio_lpc11u6x_pin_configure()
110 (config->shared->gpio_base + LPC11U6X_GPIO_REGS); in gpio_lpc11u6x_pin_configure()
111 uint8_t port_num = config->port_num; in gpio_lpc11u6x_pin_configure()
115 if (pin >= config->ngpios) { in gpio_lpc11u6x_pin_configure()
116 return -EINVAL; in gpio_lpc11u6x_pin_configure()
122 * and with no pull-down or pull-up resistor enabled. in gpio_lpc11u6x_pin_configure()
127 return -EINVAL; in gpio_lpc11u6x_pin_configure()
131 * For PIO0_0 and PIO0_[10-15] function 1 enables GPIO mode. For all in gpio_lpc11u6x_pin_configure()
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/Zephyr-Core-3.5.0/samples/subsys/usb/hid-cdc/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
150 static const char *banner0 = "\r\n"
151 "Supported commands:\r\n"
152 "up - moves the mouse up\r\n"
153 "down - moves the mouse down\r\n"
154 "right - moves the mouse to right\r\n"
155 "left - moves the mouse to left\r\n";
156 static const char *banner1 = "\r\n"
158 "it with ENTER.\r\n"
160 "when BUTTON 2 is pressed.\r\n"
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/Zephyr-Core-3.5.0/boards/shields/esp_8266/doc/
Dindex.rst3 ESP-8266 Modules
9 ESP-8266 radio is a cost-effective Wi-Fi SOC module which allows any
11 the standard IEEE802.11 b/g/n protocol, built-in complete TCP/IP protocol
15 The simplest module that uses ESP-8266 is ESP-01. This is a generic shield
16 configuration that allows any ESP-8266 module variation including ESP-12E/F.
18 .. image:: esp-01.jpg
20 :alt: ESP-01
22 Pins Assignment of the ESP-01 Module
25 +---------------+-------------------------------------+
29 +---------------+-------------------------------------+
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/Zephyr-Core-3.5.0/include/zephyr/drivers/
Dspi.h4 * SPDX-License-Identifier: Apache-2.0
25 #include <zephyr/dt-bindings/spi/spi.h>
68 * Whatever data is transmitted is looped-back to the receiving buffer of
105 /* Requests - if possible - to keep CS asserted after the transaction */
114 /* Active high logic on CS - Usually, and by default, CS logic is active
172 * gpio2: gpio@abcd0002 { ... };
176 * cs-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>,
177 * <&gpio2 20 GPIO_ACTIVE_LOW>;
179 * a: spi-dev-a@0 {
183 * b: spi-dev-b@1 {
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/Zephyr-Core-3.5.0/boards/xtensa/esp_wrover_kit/doc/
Dindex.rst3 ESP-WROVER-KIT
9 ESP-WROVER-KIT is an ESP32-based development board produced by `Espressif <https://www.espressif.co…
11 ESP-WROVER-KIT features the following integrated components:
13 - ESP32-WROVER-E module
14 - LCD screen
15 - MicroSD card slot
17 Its another distinguishing feature is the embedded FTDI FT2232HL chip - an advanced multi-interface
19 without a separate JTAG debugger. ESP-WROVER-KIT makes development convenient, easy, and
20 cost-effective.
32 The block diagram below shows the main components of ESP-WROVER-KIT and their interconnections.
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/Zephyr-Core-3.5.0/drivers/ieee802154/
Dieee802154_cc1200.c1 /* ieee802154_cc1200.c - TI CC1200 driver */
8 * SPDX-License-Identifier: Apache-2.0
40 /* ToDo: supporting 802.15.4g will require GPIO2
80 const struct cc1200_config *config = dev->config; in z_cc1200_access_reg()
118 return (spi_transceive_dt(&config->bus, &tx, &rx) == 0); in z_cc1200_access_reg()
124 return (spi_write_dt(&config->bus, &tx) == 0); in z_cc1200_access_reg()
129 struct cc1200_context *cc1200 = dev->data; in get_mac()
132 uint32_t *ptr = (uint32_t *)(cc1200->mac_addr + 4); in get_mac()
136 cc1200->mac_addr[7] = (cc1200->mac_addr[7] & ~0x01) | 0x02; in get_mac()
138 cc1200->mac_addr[4] = CONFIG_IEEE802154_CC1200_MAC4; in get_mac()
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/Zephyr-Core-3.5.0/boards/arm/mps2_an521/doc/
Dindex.rst10 on the MPS2+ AN521 board. It provides support for the MPS2+ AN521 ARM Cortex-M33
13 - Nested Vectored Interrupt Controller (NVIC)
14 - System Tick System Clock (SYSTICK)
15 - Cortex-M System Design Kit GPIO
16 - Cortex-M System Design Kit UART
31 for use with QEMU and unit tests for the ARM Cortex-M33.
37 The MPS2+ AN521 is a dual core SoC with Cortex-M33 architecture on both cores
40 both Secure and Non-Secure firmware images may be built.
44 +----------------------+-------------------------------------------------------+
47 | mps2_an521 | For building Secure (or Secure-only) firmware on CPU0 |
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