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/Zephyr-Core-3.5.0/include/zephyr/drivers/interrupt_controller/
Dintc_mchp_xec_ecia.h26 * @param girq_id is the GIRQ number (8 - 26)
27 * @param src is the interrupt source in the GIRQ (0 - 31)
35 * @param ecia_info is GIRQ connection encoded with MCHP_XEC_ECIA
42 * @param girq_id is the GIRQ number (8 - 26)
43 * @param src is the interrupt source in the GIRQ (0 - 31)
51 * @param ecia_info is GIRQ connection encoded with MCHP_XEC_ECIA
56 /* callback for ECIA GIRQ interrupt source */
62 * @param girq_id is the GIRQ number (8 - 26)
63 * @param src is the interrupt source in the GIRQ (0 - 31)
73 * @param ecia_info is GIRQ connection encoded with MCHP_XEC_ECIA
[all …]
/Zephyr-Core-3.5.0/drivers/interrupt_controller/
Dintc_mchp_ecia_xec.c81 * Enable/disable specified GIRQ's aggregated output. Aggregated output is the
82 * bit-wise or of all the GIRQ's result bits.
104 regs->GIRQ[girq_num - MCHP_FIRST_GIRQ].SRC = BIT(src_bit_pos); in mchp_xec_ecia_girq_src_clr()
116 regs->GIRQ[girq_num - MCHP_FIRST_GIRQ].EN_SET = BIT(src_bit_pos); in mchp_xec_ecia_girq_src_en()
128 regs->GIRQ[girq_num - MCHP_FIRST_GIRQ].EN_CLR = BIT(src_bit_pos); in mchp_xec_ecia_girq_src_dis()
140 regs->GIRQ[girq_num - MCHP_FIRST_GIRQ].SRC = bitmap; in mchp_xec_ecia_girq_src_clr_bitmap()
152 regs->GIRQ[girq_num - MCHP_FIRST_GIRQ].EN_SET = bitmap; in mchp_xec_ecia_girq_src_en_bitmap()
164 regs->GIRQ[girq_num - MCHP_FIRST_GIRQ].EN_CLR = bitmap; in mchp_xec_ecia_girq_src_dis_bitmap()
168 * Return read-only GIRQ result register. Result is bit-wise and of source
179 return regs->GIRQ[girq_num - MCHP_FIRST_GIRQ].RESULT; in mchp_xec_ecia_girq_result()
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DKconfig49 int "XEX GIRQ Interrupt controller init priority"
52 XEC GIRQ Interrupt controller device initialization priority.
54 So that the XEC GIRQ controllers are initialized after the
/Zephyr-Core-3.5.0/dts/bindings/interrupt-controller/
Dmicrochip,xec-ecia-girq.yaml1 description: Microchip XEC series External Interrupt Aggregator GIRQ
3 compatible: "microchip,xec-ecia-girq"
14 girq-id:
17 description: GIRQ ID number [0, 18]
23 Bit positions of each source implemented by this GIRQ.
Dmicrochip,xec-ecia.yaml18 Array of GIRQ numbers in [8, 26] whose result bits can be connected
/Zephyr-Core-3.5.0/dts/arm/microchip/mec172x/
Dmec172x-vw-routing.dtsi18 vw-girq = <24 0>;
23 vw-girq = <24 1>;
28 vw-girq = <24 2>;
33 vw-girq = <24 4>;
38 vw-girq = <24 5>;
43 vw-girq = <24 6>;
48 vw-girq = <24 8>;
53 vw-girq = <24 9>;
58 vw-girq = <24 10>;
63 vw-girq = <24 12>;
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/Zephyr-Core-3.5.0/dts/bindings/i2c/
Dmicrochip,xec-i2c.yaml19 girq:
22 description: GIRQ for this device
24 girq-bit:
27 description: Bit position in GIRQ for this device
/Zephyr-Core-3.5.0/drivers/espi/
Despi_mchp_xec_v2.h27 void (*the_isr)(int girq, int bpos, void *dev);
31 uint8_t gid; /* GIRQ id [8, 26] */
32 uint8_t gpos; /* bit position in GIRQ [0, 31] */
33 uint8_t anid; /* Aggregated GIRQ NVIC number */
34 uint8_t dnid; /* Direct GIRQ NVIC number */
/Zephyr-Core-3.5.0/dts/bindings/dma/
Dmicrochip,xec-dmac.yaml24 aggregated-girq:
28 provide the handle to the GIRQ.
37 "girq-cells":
69 girq-cells:
/Zephyr-Core-3.5.0/soc/arm/microchip_mec/mec172x/reg/
Dmec172x_ecia.h54 * Implements 19 GIRQ's. GIRQ's aggregated interrupts source into one
56 * For historical reason GIRQ's are numbered starting at 8 in the documentation.
60 * Each GIRQ is composed of 5 32-bit registers.
86 * Aggregated GIRQ NVIC mapping:
96 * Result bits in GIRQ's 13 - 21, and 23 can be directly connected to NVIC
126 /* zero based index into ECIA_Type GIRQ[] */
1118 /* GIRQ numbering */
1121 #define MCHP_GIRQ_IDX(girq) ((uint32_t)(girq) - 8u) argument
1129 /** @brief GIRQ registers. Total size = 20(0x14) bytes */
1138 /** @brief ECIA registers with each GIRQ elucidated */
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/Zephyr-Core-3.5.0/drivers/timer/
Dmchp_xec_rtos_timer.c109 * MEC GIRQ numbers are documented as 8 to 26, check and convert to zero
112 static inline void girq_src_clr(int girq, int bitpos) in girq_src_clr() argument
114 if ((girq < 8) || (girq > 26)) { in girq_src_clr()
118 ECIA_XEC_REGS->GIRQ[girq - 8].SRC = BIT(bitpos); in girq_src_clr()
121 static inline void girq_src_en(int girq, int bitpos) in girq_src_en() argument
123 if ((girq < 8) || (girq > 26)) { in girq_src_en()
127 ECIA_XEC_REGS->GIRQ[girq - 8].EN_SET = BIT(bitpos); in girq_src_en()
130 static inline void girq_src_dis(int girq, int bitpos) in girq_src_dis() argument
132 if ((girq < 8) || (girq > 26)) { in girq_src_dis()
136 ECIA_XEC_REGS->GIRQ[girq - 8].EN_CLR = BIT(bitpos); in girq_src_dis()
/Zephyr-Core-3.5.0/dts/bindings/espi/
Dmicrochip,xec-espi-vw-routing.yaml13 VW registers and ECIA GIRQ registers.
20 vw-girq:
26 to GIRQ24 b[5]. vw-girq = <24 5>;
Dmicrochip,xec-espi-saf-v2.yaml46 "#girq-cells":
54 girq-cells:
/Zephyr-Core-3.5.0/dts/arm/microchip/
Dmec172xnsz.dtsi91 compatible = "microchip,xec-ecia-girq";
94 girq-id = <0>;
102 compatible = "microchip,xec-ecia-girq";
105 girq-id = <1>;
113 compatible = "microchip,xec-ecia-girq";
116 girq-id = <2>;
124 compatible = "microchip,xec-ecia-girq";
127 girq-id = <3>;
135 compatible = "microchip,xec-ecia-girq";
138 girq-id = <4>;
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Dmec1501hsz.dtsi90 girq-id = <15>;
108 girq-id = <11>;
118 girq-id = <10>;
128 girq-id = <9>;
138 girq-id = <8>;
148 girq-id = <12>;
158 girq-id = <26>;
223 girq = <13>;
224 girq-bit = <0>;
236 girq = <13>;
[all …]
/Zephyr-Core-3.5.0/dts/bindings/spi/
Dmicrochip,xec-qmspi-ldma.yaml26 This information includes the aggregated GIRQ number, GIRQ bit
27 position, aggregated GIRQ NVIC connection, and direct NVIC
28 connection of the GIRQ bit.
/Zephyr-Core-3.5.0/include/zephyr/dt-bindings/interrupt-controller/
Dmchp-xec-ecia.h11 * g = bits[0:4], GIRQ number in [8, 26]
12 * gb = bits[12:8], peripheral source bit position [0, 31] in the GIRQ
13 * na = bits[23:16], aggregated GIRQ NVIC number
/Zephyr-Core-3.5.0/dts/bindings/gpio/
Dmicrochip,xec-gpio.yaml19 girq-id:
22 description: Aggregated GIRQ number for this bank of 32 GPIO pins.
Dmicrochip,xec-gpio-v2.yaml19 girq-id:
22 description: Aggregated GIRQ number for this bank of 32 GPIO pins.
/Zephyr-Core-3.5.0/drivers/watchdog/
Dwdt_mchp_xec.c25 uint8_t girq; member
162 mchp_soc_ecia_girq_src_clr(cfg->girq, cfg->girq_pos); in wdt_xec_isr()
185 mchp_soc_ecia_girq_src_en(cfg->girq, cfg->girq_pos); in wdt_xec_init()
200 .girq = DT_INST_PROP_BY_IDX(0, girqs, 0),
/Zephyr-Core-3.5.0/dts/bindings/crypto/
Dmicrochip,xec-symcr.yaml20 description: XEC ECIA GIRQ number and bit position.
/Zephyr-Core-3.5.0/dts/bindings/timer/
Dmicrochip,xec-rtos-timer.yaml20 description: Array of GIRQ numbers [8:26] and bit positions [0:31].
/Zephyr-Core-3.5.0/dts/bindings/led/
Dmicrochip,xec-bbled.yaml20 description: Array of pairs of GIRQ number and bit position
/Zephyr-Core-3.5.0/dts/bindings/peci/
Dmicrochip,xec-peci.yaml20 description: Array of pairs of GIRQ number and bit position
/Zephyr-Core-3.5.0/dts/bindings/watchdog/
Dmicrochip,xec-watchdog.yaml20 description: Array of GIRQ numbers [8:26] and bit positions [0:31].

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