Searched full:fsr (Results 1 – 16 of 16) sorted by relevance
| /Zephyr-latest/drivers/sensor/nxp/fxls8974/ |
| D | fxls8974.c | 284 uint8_t fsr) in fxls8974_accel_convert() argument
289 micro_ms2 = (raw * SENSOR_G) >> fsr; in fxls8974_accel_convert()
305 uint8_t fsr; in fxls8974_get_accel_data() local
309 if (cfg->ops->byte_read(dev, FXLS8974_REG_CTRLREG1, &fsr)) { in fxls8974_get_accel_data()
314 fsr = (fsr & FXLS8974_CTRLREG1_FSR_MASK) >> 1; in fxls8974_get_accel_data()
315 switch (fsr) { in fxls8974_get_accel_data()
317 fsr = 10U; in fxls8974_get_accel_data()
320 fsr = 9U; in fxls8974_get_accel_data()
323 fsr = 8U; in fxls8974_get_accel_data()
326 fsr = 7U; in fxls8974_get_accel_data()
[all …]
|
| /Zephyr-latest/arch/riscv/core/ |
| D | asm_macros.inc | 39 .macro fsr, rs, mem
49 .macro fsr, rs, mem
|
| /Zephyr-latest/dts/bindings/sensor/ |
| D | ti,ina219.yaml | 28 0 = 16 V FSR
29 1 = 32 V FSR
|
| /Zephyr-latest/drivers/serial/ |
| D | uart_renesas_rz_scif.c | 59 const uint32_t fsr = reg->FSR; in uart_rz_scif_err_check() local
66 if ((fsr & R_SCIFA0_FSR_PER_Msk) != 0) { in uart_rz_scif_err_check()
69 if ((fsr & R_SCIFA0_FSR_FER_Pos) != 0) { in uart_rz_scif_err_check()
|
| /Zephyr-latest/arch/sparc/core/ |
| D | interrupt_trap.S | 130 * 1. Store FSR to memory. This has the side-effect of completing all
139 st %fsr, [%sp]
228 st %fsr, [%sp + 64 + 0x80]
246 ld [%sp + 64 + 0x80], %fsr
|
| /Zephyr-latest/modules/cmsis/ |
| D | cmsis_core_a_r_ext.h | 21 /* FSR Register Definitions */
|
| /Zephyr-latest/arch/xtensa/core/offsets/ |
| D | offsets.c | 45 GEN_OFFSET_SYM(_xtensa_irq_bsa_t, fsr);
|
| /Zephyr-latest/tests/kernel/fpu_sharing/generic/src/ |
| D | float_regs_xtensa.h | 47 __asm__ volatile("wur.fsr %0\n" :: "r"(regs->fp_non_volatile.reg[16])); in _load_all_float_registers()
80 __asm__ volatile("rur.fsr %0\n" : "=r"(regs->fp_non_volatile.reg[16])); in _store_all_float_registers()
|
| /Zephyr-latest/arch/xtensa/include/ |
| D | xtensa_asm2_context.h | 95 uintptr_t fsr; member
|
| D | xtensa_asm2_s.h | 105 * called FCR and FSR.The FR register file consists of 16 registers of
111 rur.fsr a0
135 wur.fsr a0
|
| /Zephyr-latest/arch/xtensa/core/ |
| D | crt1.S | 65 * CPENABLE, FP's FCR and FSR, EXCSAVE[n]
|
| /Zephyr-latest/arch/xtensa/core/startup/ |
| D | reset_vector.S | 581 # define FSR 233 macro
587 wur a0, FSR /* clear FSR */
|
| /Zephyr-latest/soc/atmel/sam/sam4l/ |
| D | soc.c | 150 return ((HFLASHC->FSR & FLASHCALW_FSR_FRDY) != 0); in flashcalw_is_ready()
|
| /Zephyr-latest/drivers/flash/ |
| D | flash_sam.c | 116 /* FSR register is cleared on read */ in sam_flash_section_wait_until_ready()
|
| /Zephyr-latest/drivers/sensor/tdk/icm42670/ |
| D | icm42670.c | 488 LOG_ERR("Failed to configure accel FSR"); in icm42670_turn_on_sensor()
498 LOG_ERR("Failed to configure gyro FSR"); in icm42670_turn_on_sensor()
|
| /Zephyr-latest/arch/arm/core/cortex_m/ |
| D | fault.c | 763 "Fault escalation without FSR info"); in hard_fault()
|
