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/Zephyr-latest/soc/nxp/kinetis/ke1xz/
Dsoc.c64 /* Fast Internal Reference Clock (FIRC) configuration */
66 "Invalid SCG FIRC divider 2 value");
79 #error Invalid SCG FIRC clock frequency
96 /* Temporary switch to safe SIRC in order to configure FIRC */ in clk_init()
/Zephyr-latest/soc/openisa/rv32m1/
Dsoc.c30 * Run-mode configuration for the fast internal reference clock (FIRC).
42 * FIRC-based system clock configuration.
228 /* Switch to SIRC so we can initialize the FIRC. */ in soc_early_init_hook()
231 /* Now that we're running off of SIRC, set up and switch to FIRC. */ in soc_early_init_hook()
/Zephyr-latest/soc/nxp/kinetis/ke1xf/
Dsoc.c98 /* Fast Internal Reference Clock (FIRC) configuration */
100 "Invalid SCG FIRC divider 1 value");
102 "Invalid SCG FIRC divider 2 value");
116 #error Invalid SCG FIRC clock frequency
166 /* Temporary switch to safe SIRC in order to configure FIRC */ in clk_init()
/Zephyr-latest/dts/bindings/power/
Dnxp,s32k3-pmc.yaml28 When configuring system clocks higher than FIRC clock frequency,
/Zephyr-latest/soc/nxp/mcx/mcxw/
Dsoc.c60 /* Configuration to set FIRC to maximum frequency */ in clock_init()
63 .range = kSCG_FircRange96M, /* 96 Mhz FIRC clock selected */ in clock_init()
/Zephyr-latest/boards/nxp/frdm_ke15z/doc/
Dindex.rst59 The KE15 SoC is configured to run at 48 MHz using the FIRC.
/Zephyr-latest/boards/nxp/frdm_ke17z/doc/
Dindex.rst78 The KE17Z SoC is configured to run at 48 MHz using the FIRC.
/Zephyr-latest/boards/nxp/frdm_ke17z512/doc/
Dindex.rst80 The KE17Z9 SoC is configured to run at 48 MHz using the FIRC.
/Zephyr-latest/boards/openisa/rv32m1_vega/doc/
Dindex.rst319 the system timer, and the fast internal reference clock (FIRC) to generate a