1# Copyright (C) 2020 Gerson Fernando Budke <nandojve@gmail.com>
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5    GPIO pins exposed on Atmel Xplained Pro headers.
6
7    The Xplained Pro layout provide a standard 20 pin header.  A board can have
8    one or more headers and can share pins.  The extension headers are given
9    names EXTn where n ϵ [1…7], n is determined by which ID pin is connected
10    to the embedded debugger.  A header with ID7 signal from the embedded
11    debugger connected should be called EXT7. PWR, EXT1, EXT2 and EXT3 are
12    standard extension headers that have a predefined position according to the
13    list below:
14      * PWR is right angled at the top right hand side of the board. This
15      header must always be implemented.
16      * EXT1 is right angled at the top right hand side of the board, located
17      below the PWR header. This header must always be present.
18      * EXT2 is right angled and at the bottom right hand side of the board.
19      This header is mandatory for medium and large boards and should not be
20      implemented on small boards.
21      * EXT3 is right angled pointing downwards
22    All MCU boards have to implement at least PWR, EXT1, EXT2 (on medium and
23    large boards), and EXT3. EXT4 to EXT7 can be placed differently depending
24    on the board design. EXT4 to EXT7 can either be standard extension headers
25    or application specific headers.
26
27    Documentation:
28    https://www.microchip.com/development-tools/xplained-boards
29    http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-42091-Atmel-Xplained-Pro-Hardware-Development-Kit_User%20Guide.pdf
30
31    This binding provides a nexus mapping for 20 pins where pins are disposed
32    to have a even and odd column:
33
34                           Connector
35    Bind      Pin Name     Pin   Pin  Pin Name        Bind
36                       ID  1       2  GND
37      0            ADC(+)  3       4  ADC(-)           1
38      2   UART(RTS)/GPIO1  5       6  UART(CTS)/GPIO2  3
39      4            PWM(+)  7       8  PWM(-)           5
40      6         IRQ/GPIO3  9      10  SPI(CS1)/GPIO4   7
41      8          I2C(SDA)  11     12  I2C(SCL)         9
42     10          UART(RX)  13     14  UART(TX)         11
43     12          SPI(CS0)  15     16  SPI(MOSI)        13
44     14         SPI(MISO)  17     18  SPI(SCK)         15
45                      GND  19     20  VDD(+3.3V)
46
47compatible: "atmel-xplained-pro-header"
48
49include: [gpio-nexus.yaml, base.yaml]
50