Searched full:emio (Results 1 – 8 of 8) sorted by relevance
7 Xilinx Zynq-7000/ZynqMP MIO/EMIO GPIO controller node.13 logic part of the SoC (EMIO pins).21 * Bank 2: EMIO pins [31:00]22 * Bank 3: EMIO pins [63:32] (total: 64 EMIO pins)28 * Bank 3: EMIO pins [31:00]29 * Bank 4: EMIO pins [63:32]30 * Bank 5: EMIO pins [95:64] (total: 96 EMIO pins)
7 Xilinx Zynq-7000/ZynqMP MIO/EMIO GPIO controller bank node.10 a bank of the MIO/EMIO GPIO controller integrated in the Processor
2 # Xilinx Processor System MIO / EMIO GPIO controller driver10 bool "Xilinx Processor System MIO / EMIO GPIO controller driver"15 Enable the Xilinx Processor System MIO / EMIO GPIO controller driver.
2 * Xilinx Processor System MIO / EMIO GPIO controller driver47 * This struct contains all data of a PS MIO / EMIO GPIO bank61 * This struct contains all data of a PS MIO / EMIO GPIO bank
2 * Xilinx Processor System MIO / EMIO GPIO controller driver37 * status and data acquisition of each MIO / EMIO GPIO pin associated with74 * IRQ. The ISR iterates all associated MIO / EMIO GPIO pink bank167 * Register & initialize all instances of the Processor System's MIO / EMIO GPIO
2 * Xilinx Processor System MIO / EMIO GPIO controller driver
2 * Xilinx Processor System MIO / EMIO GPIO controller driver30 * Configures an individual pin within a MIO / EMIO GPIO pin bank.420 * @brief Initialize a MIO / EMIO GPIO bank sub-device422 * Initialize a MIO / EMIO GPIO bank sub-device, which is a child451 /* MIO / EMIO bank device definition macros */466 /* Register & initialize all MIO / EMIO GPIO banks specified in the device tree. */
504 * Added Xilinx PS MIO/EMIO GPIO controller driver.
