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/Zephyr-latest/include/zephyr/drivers/interrupt_controller/
Dintc_eirq_nxp_s32.h15 /** NXP SIUL2 EIRQ callback */
19 * @brief NXP SIUL2 EIRQ pin activation type
33 * @param dev SIUL2 EIRQ device
41 * @param dev SIUL2 EIRQ device
56 * @param dev SIUL2 EIRQ device
66 * @param dev SIUL2 EIRQ device
74 * @param dev SIUL2 EIRQ device
/Zephyr-latest/dts/bindings/gpio/
Dnxp,s32-gpio.yaml8 to either the SIUL2 EIRQ interrupt controller or, when available on the SoC,
10 SIUL2 EIRQ interrupt controller.
53 respective external interrupt lines (<gpio-pin eirq-line>).
/Zephyr-latest/drivers/interrupt_controller/
Dintc_irqmp.c58 return DT_INST_PROP(0, eirq); in get_irqmp_eirq()
96 const int eirq = get_irqmp_eirq(); in z_sparc_int_get_source() local
99 if ((eirq != 0) && (irl == eirq)) { in z_sparc_int_get_source()
/Zephyr-latest/dts/bindings/interrupt-controller/
Dnxp,s32-siul2-eirq.yaml7 compatible: "nxp,s32-siul2-eirq"
64 - eirq-line
Dgaisler,irqmp.yaml14 eirq:
/Zephyr-latest/dts/sparc/gaisler/
Dleon3soc.dtsi35 eirq = <0>;
Dgr716a.dtsi41 eirq = <1>;
/Zephyr-latest/boards/nxp/mr_canhubk3/doc/
Dindex.rst72 to either the SIUL2 EIRQ or WKPU interrupt controllers, as supported by the SoC.
73 By default, GPIO interrupts are routed to SIUL2 EIRQ interrupt controller,
/Zephyr-latest/dts/arm/nxp/
Dnxp_s32z27x_r52.dtsi220 compatible = "nxp,s32-siul2-eirq";
271 compatible = "nxp,s32-siul2-eirq";
346 compatible = "nxp,s32-siul2-eirq";
419 compatible = "nxp,s32-siul2-eirq";
Dnxp_s32k344_m7.dtsi90 eirq0: eirq@40290010 {
91 compatible = "nxp,s32-siul2-eirq";
/Zephyr-latest/doc/releases/
Drelease-notes-3.3.rst1376 - :dtcompatible:`nxp,s32-siul2-eirq`