Searched full:ec (Results 1 – 25 of 145) sorted by relevance
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13 * Byte codes returned by EC over SPI interface.15 * These can be used by the AP to debug the EC interface, and to determine16 * when the EC is not in a state where it will ever get around to responding19 * Example of sequence of bytes read from EC for a current good transfer:22 * 3. - - EC starts handling CS# interrupt24 * 5. EC_SHI_PROCESSING - EC starts processing request; AP is clocking in26 * 6. - - EC finishes processing and sets up response31 * 11 - - EC processes CS# interrupt and sets up DMA for41 * Then the EC found an error in the request, or was not ready for the request43 * because the EC is unable to tell when the AP is done sending its request.[all …]
1 -----BEGIN EC PARAMETERS-----3 -----END EC PARAMETERS-----4 -----BEGIN EC PRIVATE KEY-----8 -----END EC PRIVATE KEY-----
1 # Google Kukui EC7 bool "Google Kukui EC"10 This is the EC (Embedded Controller) inside a Lenovo Chromebook11 Duet and 10e Chromebook Tablet. The EC handles battery charging,
12 model = "Google Kukui EC";13 compatible = "google,kukui-ec", "st,stm32f098";
1 # Google Kukui EC
2 name: Google Kukui EC
40 /* ACPI_PM1 RT/EC Status 1 */45 /* ACPI_PM1 RT/EC Status 2 */55 /* ACPI_PM1 RT/EC Enable 1 */60 /* ACPI_PM1 RT/EC Enable 2 */68 /* ACPI_PM1 RT/EC Control 1 */73 /* ACPI_PM1 RT/EC Control 2 */82 /* ACPI_PM1 RT/EC Control 21 */87 /* ACPI_PM1 RT/EC Control 22 */92 /* ACPI_PM1 EC PM Status register */97 /** @brief ACPI EC Registers (ACPI_EC) */
7 bool "Nuvoton NPCX embedded controller (EC) ESPI driver"18 This is the port size used by the Host and EC to communicate over20 notice the valid value in npcx ec series for this option is 8/16/32/24 int "Host I/O peripheral port size for ec host command in npcx series"28 This is the port size used by the Host and EC to communicate over30 Please notice the valid value in npcx ec series for this option is48 EC can accept 1/2/4 bytes of Port 80 data written from the Host in an
109 This is the port number used by the Host and EC to communicate over120 bool "Host peripheral device support EC host command subsystem"122 Enables Embedded Controller (EC) host command subsystem via eSPI136 This is the port number used by the Host and EC to communicate over149 hex "Host I/O peripheral port number for ec host command data"153 This is the port number used by the Host and EC to communicate over154 the eSPI peripheral channel to send EC host command data and its160 hex "Host I/O peripheral port number for ec host command parameters"164 This is the port number used by the Host and EC to communicate over
91 This is the port size used by the Host and EC to communicate over95 int "Host I/O peripheral port size for ec host command in MEC172X series"99 This is the port size used by the Host and EC to communicate over114 bool "SoC ACPI EC 2 over eSPI"120 bool "SoC ACPI EC 3 over eSPI"126 bool "SoC ACPI EC 4 over eSPI"172 bool "Read ACPI EC Event Data in IBF ISR"175 Enable reading event data in ACPI EC IBF ISR. This is used in OS
28 prompt "H2RAM space for ec host command"125 With this option enabled, EC will send IRQ12 signal to host when the
7 """Script to pack EC binary with manifest header.9 Package ecos main FW binary (kernel) and AON task binary into final EC binary25 help="EC kernel binary to pack, \26 usually ec.RW.bin or ec.RW.flat.",29 help="EC aontask binary to pack, \58 print(" Packing EC image file for ISH")
17 module-str = ec-host-commands21 int "Stack size for the EC host command handler thread"25 int "Buffer size in bytes for TX buffer shared by all EC host commands"38 int "Buffer size in bytes for RX buffer shared by all EC host commands"
34 follow the `Chromium EC Flashing Documentation`_.49 .. _Chromium EC Flashing Documentation:50 https://chromium.googlesource.com/chromiumos/platform/ec#Flashing-via-the-servo-debug-board
21 when the interrupt is triggered in EC low power mode, it can wakeup22 EC or not. Via this controller, we set the wakeup trigger edge,
111 * ECINDAR3-0 are EC-indirect memory address registers. in ramcode_flash_follow_mode()124 /* Writing 0 to EC-indirect memory data register */ in ramcode_flash_follow_mode()157 /* Writing 0 to EC-indirect memory data register */ in ramcode_flash_fsce_high()220 /* enter EC-indirect follow mode */ in ramcode_flash_cmd_write_enable()226 /* exit EC-indirect follow mode */ in ramcode_flash_cmd_write_enable()234 /* enter EC-indirect follow mode */ in ramcode_flash_cmd_write_disable()240 /* exit EC-indirect follow mode */ in ramcode_flash_cmd_write_disable()275 /* enter EC-indirect follow mode */ in ramcode_flash_cmd_write()309 /* exit EC-indirect follow mode */ in ramcode_flash_cmd_write()325 /* enter EC-indirect follow mode */ in ramcode_flash_cmd_erase()[all …]
30 uint64_t tm, ts, ec, ret; in main() local68 tgpio_pin_read_ts_ec(tgpio_dev, TGPIO_PIN_IN, &ts, &ec); in main()69 printk("[TGPIO] timestamp: %016llx, event count: %016llx\n", ts, ec); in main()
3 Google Kukui EC13 Zephyr has support for the STM32-based embedded controller (EC) on-board.75 `Chromium EC Flashing Documentation`_ for more information.87 .. _Chromium EC Flashing Documentation:88 https://chromium.googlesource.com/chromiumos/platform/ec#Flashing-via-the-servo-debug-board
87 * EC div = 6 (FND / 6 = 8 mhz)119 /* JTAG and EC */ in chip_run_pll_sequence()213 * interrupt to restore clocks. With this interrupt, EC will not defer in riscv_idle()228 * it means that EC waked-up by the above issue not an in riscv_idle()251 * The EC processor(CPU) cannot be in the k_cpu_idle() during in arch_cpu_idle()253 * the EC processor would be clock gated. in arch_cpu_idle()298 /* bit3: UART1 belongs to the EC side. */ in ite_it8xxx2_init()316 /* bit3: UART2 belongs to the EC side. */ in ite_it8xxx2_init()
6 tags: ec
170 * low-frequency timer before ec entered deep idle state.176 * system timer by low-frequency timer after ec left deep idle state.189 * @brief Function to configure system sleep settings. After ec received "wfi"190 * instruction, ec will enter sleep/deep sleep state for better power193 * @param is_deep A boolean indicating ec enters deep sleep or sleep state
57 If bits[14:2] of the address written by the Host to the EC address59 of the EC address selects which of the two memory regions is accessed.
2 * Copyright (c) 2023 Kenneth J. Miller <ken@miller.ec>
63 on-chip PLL to generate a resulting EC clock rate of 15 MHz. See Processor clock86 `Chromium EC Flashing Documentation`_ for more information.106 .. _Chromium EC Flashing Documentation:107 https://chromium.googlesource.com/chromiumos/platform/ec#Flashing-via-the-servo-debug-board
1 # Nuvoton NPCX4 EC series
