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18 #define ZEPHYR_INCLUDE_SYS_UTIL_INTERNAL_UTIL_DEC_H_20 #define Z_UTIL_DEC_0 021 #define Z_UTIL_DEC_1 022 #define Z_UTIL_DEC_2 123 #define Z_UTIL_DEC_3 224 #define Z_UTIL_DEC_4 325 #define Z_UTIL_DEC_5 426 #define Z_UTIL_DEC_6 527 #define Z_UTIL_DEC_7 628 #define Z_UTIL_DEC_8 7[all …]
18 #define ZEPHYR_INCLUDE_SYS_UTIL_INTERNAL_UTIL_INC_H_20 #define Z_UTIL_INC_0 121 #define Z_UTIL_INC_1 222 #define Z_UTIL_INC_2 323 #define Z_UTIL_INC_3 424 #define Z_UTIL_INC_4 525 #define Z_UTIL_INC_5 626 #define Z_UTIL_INC_6 727 #define Z_UTIL_INC_7 828 #define Z_UTIL_INC_8 9[all …]
18 #define ZEPHYR_INCLUDE_SYS_UTIL_INTERNAL_UTIL_X2_H_20 #define Z_UTIL_X2_0 021 #define Z_UTIL_X2_1 222 #define Z_UTIL_X2_2 423 #define Z_UTIL_X2_3 624 #define Z_UTIL_X2_4 825 #define Z_UTIL_X2_5 1026 #define Z_UTIL_X2_6 1227 #define Z_UTIL_X2_7 1428 #define Z_UTIL_X2_8 16[all …]
8 #define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP32_GPIO_SIGMAP_H_10 #define ESP_NOSIG ESP_SIG_INVAL12 #define ESP_SPICLK_IN 013 #define ESP_SPICLK_OUT 014 #define ESP_SPIQ_IN 115 #define ESP_SPIQ_OUT 116 #define ESP_SPID_IN 217 #define ESP_SPID_OUT 218 #define ESP_SPIHD_IN 319 #define ESP_SPIHD_OUT 3[all …]
8 #define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP32S3_GPIO_SIGMAP_H_10 #define ESP_NOSIG ESP_SIG_INVAL12 #define ESP_SPIQ_IN 013 #define ESP_SPIQ_OUT 014 #define ESP_SPID_IN 115 #define ESP_SPID_OUT 116 #define ESP_SPIHD_IN 217 #define ESP_SPIHD_OUT 218 #define ESP_SPIWP_IN 319 #define ESP_SPIWP_OUT 3[all …]
8 #define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP32S2_GPIO_SIGMAP_H_10 #define ESP_NOSIG ESP_SIG_INVAL12 #define ESP_SPICLK_OUT ESP_SPICLK_OUT_MUX13 #define ESP_CLK_I2S ESP_CLK_I2S_MUX14 #define ESP_FSPICLK_OUT ESP_FSPICLK_OUT_MUX16 #define ESP_SPIQ_IN 017 #define ESP_SPIQ_OUT 018 #define ESP_SPID_IN 119 #define ESP_SPID_OUT 120 #define ESP_SPIHD_IN 2[all …]
8 #define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP32C3_GPIO_SIGMAP_H_10 #define ESP_NOSIG ESP_SIG_INVAL12 #define ESP_SPICLK_OUT_MUX ESP_SPICLK_OUT13 #define ESP_SPIQ_IN 014 #define ESP_SPIQ_OUT 015 #define ESP_SPID_IN 116 #define ESP_SPID_OUT 117 #define ESP_SPIHD_IN 218 #define ESP_SPIHD_OUT 219 #define ESP_SPIWP_IN 3[all …]
7 #define VALKYRIE_IRQ_H9 #define SPI_RESERVED7_7 23910 #define SPI_RESERVED7_6 23811 #define SPI_RESERVED7_5 23712 #define SPI_RESERVED7_4 23613 #define SPI_RESERVED7_3 23514 #define SPI_RESERVED7_2 23415 #define SPI_RESERVED7_1 23316 #define SPI_RESERVED7_0 23217 #define SPI_RESERVED6_13 231[all …]
16 #define __SOC_GPIO_H_18 #define REG_PAD_OWNER_BASE 0x002019 #define REG_GPI_INT_STS_BASE 0x010020 #define PAD_CFG0_PMODE_MASK (0x0F << 10)22 #define APL_GPIO_DEV_N_0 DT_NODELABEL(gpio_n_000_031)23 #define APL_GPIO_0 024 #define APL_GPIO_1 125 #define APL_GPIO_2 226 #define APL_GPIO_3 327 #define APL_GPIO_4 4[all …]
8 #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_S32Z2_CLOCK_H_10 #define NXP_S32_FIRC_CLK 1U11 #define NXP_S32_FXOSC_CLK 2U12 #define NXP_S32_SIRC_CLK 3U13 #define NXP_S32_COREPLL_CLK 4U14 #define NXP_S32_PERIPHPLL_CLK 5U15 #define NXP_S32_DDRPLL_CLK 6U16 #define NXP_S32_LFAST0_PLL_CLK 7U17 #define NXP_S32_LFAST1_PLL_CLK 8U18 #define NXP_S32_COREPLL_PHI0_CLK 9U[all …]
8 #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_S32K344_CLOCK_H_10 #define NXP_S32_FIRC_CLK 1U11 #define NXP_S32_FIRC_STANDBY_CLK 2U12 #define NXP_S32_SIRC_CLK 3U13 #define NXP_S32_SIRC_STANDBY_CLK 4U14 #define NXP_S32_FXOSC_CLK 5U15 #define NXP_S32_SXOSC_CLK 6U16 #define NXP_S32_PLL_CLK 7U17 #define NXP_S32_PLL_POSTDIV_CLK 8U18 #define NXP_S32_PLL_PHI0_CLK 9U[all …]
6 #define INCLUDE_ZEPHYR_DT_BINDINGS_GPIO_ST_MORPHO_HEADER_H_9 #define ST_MORPHO_PIN_MASK 0xFF15 #define ST_MORPHO_L_1 016 #define ST_MORPHO_L_2 117 #define ST_MORPHO_L_3 218 #define ST_MORPHO_L_4 319 #define ST_MORPHO_L_5 420 #define ST_MORPHO_L_6 521 #define ST_MORPHO_L_7 622 #define ST_MORPHO_L_8 7[all …]
52 #define __SYSTEM_H_63 #define ALT_CPU_ARCHITECTURE "altera_nios2_gen2"64 #define ALT_CPU_BIG_ENDIAN 065 #define ALT_CPU_BREAK_ADDR 0x0020082066 #define ALT_CPU_CPU_ARCH_NIOS2_R167 #define ALT_CPU_CPU_FREQ 50000000u68 #define ALT_CPU_CPU_ID_SIZE 169 #define ALT_CPU_CPU_ID_VALUE 0x0000000070 #define ALT_CPU_CPU_IMPLEMENTATION "fast"71 #define ALT_CPU_DATA_ADDR_WIDTH 0x1c[all …]
8 #define ZEPHYR_DRIVERS_SENSOR_ICM42605_ICM42605_REG_H_11 #define REG_DEVICE_CONFIG 0x1112 #define REG_DRIVE_CONFIG 0x1313 #define REG_INT_CONFIG 0x1414 #define REG_FIFO_CONFIG 0x1615 #define REG_TEMP_DATA1 0x1D16 #define REG_TEMP_DATA0 0x1E17 #define REG_ACCEL_DATA_X1 0x1F18 #define REG_ACCEL_DATA_X0 0x2019 #define REG_ACCEL_DATA_Y1 0x21[all …]
8 #define __DSA_KSZ8794_H__11 #define KSZ8794_SPI_CMD_WR (BIT(6))12 #define KSZ8794_SPI_CMD_RD (BIT(6) | BIT(5))15 #define KSZ8794_BMCR 0x0016 #define KSZ8794_BMSR 0x0117 #define KSZ8794_PHYID1 0x0218 #define KSZ8794_PHYID2 0x0319 #define KSZ8794_ANAR 0x0420 #define KSZ8794_ANLPAR 0x0521 #define KSZ8794_LINKMD 0x1D[all …]
14 #define _ENC424J600_17 #define ENC424J600_SFR0_ETXSTL 0x0018 #define ENC424J600_SFR0_ETXSTH 0x0119 #define ENC424J600_SFR0_ETXLENL 0x0220 #define ENC424J600_SFR0_ETXLENH 0x0321 #define ENC424J600_SFR0_ERXSTL 0x0422 #define ENC424J600_SFR0_ERXSTH 0x0523 #define ENC424J600_SFR0_ERXTAILL 0x0624 #define ENC424J600_SFR0_ERXTAILH 0x0725 #define ENC424J600_SFR0_ERXHEADL 0x08[all …]
8 #define __DSA_KSZ8863_H__11 #define KSZ8863_SPI_CMD_WR (BIT(6))12 #define KSZ8863_SPI_CMD_RD (BIT(6) | BIT(5))15 #define KSZ8863_BMCR 0x0016 #define KSZ8863_BMSR 0x0117 #define KSZ8863_PHYID1 0x0218 #define KSZ8863_PHYID2 0x0319 #define KSZ8863_ANAR 0x0420 #define KSZ8863_ANLPAR 0x0521 #define KSZ8863_LINKMD 0x1D[all …]
7 #define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ITE_INTC_H_9 #define IRQ_TYPE_NONE 010 #define IRQ_TYPE_EDGE_RISING 111 #define IRQ_TYPE_EDGE_FALLING 212 #define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)13 #define IRQ_TYPE_LEVEL_HIGH 414 #define IRQ_TYPE_LEVEL_LOW 818 #define IT8XXX2_IRQ_WU20 119 #define IT8XXX2_IRQ_KBC_OBE 220 #define IT8XXX2_IRQ_SMB_D 4[all …]
10 #define ZEPHYR_DRIVERS_IEEE802154_IEEE802154_RF2XX_REGS_H_13 #define RF2XX_AES_BLOCK_SIZE 1614 #define RF2XX_AES_CORE_CYCLE_TIME 24 /* us */15 #define RF2XX_RANDOM_NUMBER_UPDATE_INTERVAL 1 /* us */16 #define RX2XX_FRAME_HEADER_SIZE 217 #define RX2XX_FRAME_FOOTER_SIZE 318 #define RX2XX_FRAME_FCS_LENGTH 219 #define RX2XX_FRAME_MIN_PHR_SIZE 520 #define RX2XX_FRAME_PHR_INDEX 121 #define RX2XX_FRAME_LQI_INDEX 2[all …]
9 #define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_INTEL_SOCFPGA_RESET_H_25 #define RSTMGR_SDMCOLDRST_RSTLINE 026 #define RSTMGR_SDMWARMRST_RSTLINE 127 #define RSTMGR_SDMLASTPORRST_RSTLINE 228 #define RSTMGR_L4WD0RST_RSTLINE 1629 #define RSTMGR_L4WD1RST_RSTLINE 1730 #define RSTMGR_L4WD2RST_RSTLINE 1831 #define RSTMGR_L4WD3RST_RSTLINE 1932 #define RSTMGR_L4WD4RST_RSTLINE 2033 #define RSTMGR_DEBUGRST_RSTLINE 21[all …]
8 #define _MEC172X_ECIA_H14 #define ECIA_BASE_ADDR DT_REG_ADDR(DT_NODELABEL(ecia))16 #define MCHP_FIRST_GIRQ_NOS 8u17 #define MCHP_LAST_GIRQ_NOS 26u23 #define MCHP_ECIA_GIRQ_CLK_WAKE_ONLY 22u25 #define MCHP_ECIA_AGGR_BITMAP (BIT(8) | BIT(9) | BIT(10) | BIT(11) | \29 #define MCHP_ECIA_DIRECT_BITMAP (BIT(13) | BIT(14) | BIT(15) | BIT(16) | \33 #define MCHP_ECIA_ALL_BITMAP GENMASK(26, 8)36 #define MCHP_NVIC_NUM_PRI_BITS 3u37 #define MCHP_NVIC_PRI_LO_VAL 7u[all …]
16 #define ZEPHYR_INCLUDE_ARCH_ARC_V2_AUX_REGS_H_18 #define _ARC_V2_LP_START 0x00219 #define _ARC_V2_LP_END 0x00320 #define _ARC_V2_IDENTITY 0x00421 #define _ARC_V2_SEC_STAT 0x0922 #define _ARC_V2_STATUS32 0x00a23 #define _ARC_V2_STATUS32_P0 0x00b24 #define _ARC_V2_USER_SP 0x00d25 #define _ARC_V2_AUX_IRQ_CTRL 0x00e26 #define _ARC_V2_IC_IVIC 0x010[all …]
12 #define ZEPHYR_DRIVERS_SENSOR_LSM6DSL_LSM6DSL_H_28 #define LSM6DSL_REG_FUNC_CFG_ACCESS 0x0129 #define LSM6DSL_MASK_FUNC_CFG_EN BIT(7)30 #define LSM6DSL_SHIFT_FUNC_CFG_EN 731 #define LSM6DSL_MASK_FUNC_CFG_EN_B BIT(5)32 #define LSM6DSL_SHIFT_FUNC_CFG_EN_B 534 #define LSM6DSL_REG_SENSOR_SYNC_TIME_FRAME 0x0435 #define LSM6DSL_MASK_SENSOR_SYNC_TIME_FRAME_TPH (BIT(3) | BIT(2) | \37 #define LSM6DSL_SHIFT_SENSOR_SYNC_TIME_FRAME_TPH 039 #define LSM6DSL_REG_SENSOR_SYNC_RES_RATIO 0x05[all …]
8 #define ZEPHYR_DRIVERS_FLASH_OSPI_STM32_H_12 #define NbData DataLength13 #define AddressSize AddressWidth14 #define InstructionDtrMode InstructionDTRMode15 #define AddressDtrMode AddressDTRMode16 #define DataDtrMode DataDTRMode17 #define InstructionSize InstructionWidth18 #define FifoThreshold FifoThresholdByte19 #define ChipSelectHighTime ChipSelectHighTimeCycle20 #define FlashId IOSelect[all …]
12 #define ZEPHYR_DRIVERS_SENSOR_LSM6DS0_LSM6DS0_H_18 #define LSM6DS0_REG_ACT_THS 0x0419 #define LSM6DS0_MASK_ACT_THS_SLEEP_ON_INACT_EN BIT(7)20 #define LSM6DS0_SHIFT_ACT_THS_SLEEP_ON_INACT_EN 721 #define LSM6DS0_MASK_ACT_THS_ACT_THS (BIT(6) | BIT(5) | BIT(4) | \24 #define LSM6DS0_SHIFT_ACT_THS_ACT_THS 026 #define LSM6DS0_REG_ACT_DUR 0x0528 #define LSM6DS0_REG_INT_GEN_CFG_XL 0x0629 #define LSM6DS0_MASK_INT_GEN_CFG_XL_AOI_XL BIT(7)30 #define LSM6DS0_SHIFT_INT_GEN_CFG_XL_AOI_XL 7[all …]
